Rebase from upstream commit : 3bb9dcf44627ffdd313fe92c563ae454b6ff8aa6

[librecmc/librecmc.git] / target / linux / generic / pending-3.18 / 132-mips_inline_dma_ops.patch

diff --git a/target/linux/generic/pending-3.18/132-mips_inline_dma_ops.patch b/target/linux/generic/pending-3.18/132-mips_inline_dma_ops.patch
index c008aea41dec5475b693111ccc116dc4de790c28..7a64ae7994676b25b0836f2b36bf634c5c239da3 100644 (file)
--- a/target/linux/generic/pending-3.18/132-mips_inline_dma_ops.patch
+++ b/target/linux/generic/pending-3.18/132-mips_inline_dma_ops.patch
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1450,6 +1450,7 @@ config CPU_CAVIUM_OCTEON
+@@ -1453,6 +1453,7 @@ config CPU_CAVIUM_OCTEON
        select CPU_SUPPORTS_HUGEPAGES
        select USB_EHCI_BIG_ENDIAN_MMIO
        select MIPS_L1_CACHE_SHIFT_7
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
        help
          The Cavium Octeon processor is a highly integrated chip containing
          many ethernet hardware widgets for networking tasks. The processor
-@@ -1705,6 +1706,9 @@ config MIPS_MALTA_PM
+@@ -1708,6 +1709,9 @@ config MIPS_MALTA_PM
        bool
        default y