+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -43,8 +43,8 @@ static void early_nvram_init(void)
+ #ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ mcore_ssb = &bcm47xx_bus.ssb.mipscore;
+- base = mcore_ssb->flash_window;
+- lim = mcore_ssb->flash_window_size;
++ base = mcore_ssb->pflash.window;
++ lim = mcore_ssb->pflash.window_size;
+ break;
+ #endif
+ #ifdef CONFIG_BCM47XX_BCMA
+--- a/arch/mips/bcm47xx/wgt634u.c
++++ b/arch/mips/bcm47xx/wgt634u.c
+@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
+ SSB_CHIPCO_IRQ_GPIO);
+ }
+
+- wgt634u_flash_data.width = mcore->flash_buswidth;
+- wgt634u_flash_resource.start = mcore->flash_window;
+- wgt634u_flash_resource.end = mcore->flash_window
+- + mcore->flash_window_size
++ wgt634u_flash_data.width = mcore->pflash.buswidth;
++ wgt634u_flash_resource.start = mcore->pflash.window;
++ wgt634u_flash_resource.end = mcore->pflash.window
++ + mcore->pflash.window_size
+ - 1;
+ return platform_add_devices(wgt634u_devices,
+ ARRAY_SIZE(wgt634u_devices));
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
+
+ If unsure, say N
+
++config SSB_SFLASH
++ bool "SSB serial flash support"
++ depends on SSB_DRIVER_MIPS && BROKEN
++ default y
++
+ # Assumption: We are on embedded, if we compile the MIPS core.
+ config SSB_EMBEDDED
+ bool
+@@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
+
+ If unsure, say N
+
++config SSB_DRIVER_GPIO
++ bool "SSB GPIO driver"
++ depends on SSB && GPIOLIB
++ help
++ Driver to provide access to the GPIO pins on the bus.
++
++ If unsure, say N
++
+ endmenu
+--- a/drivers/ssb/Makefile
++++ b/drivers/ssb/Makefile
+@@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
+ # built-in drivers
+ ssb-y += driver_chipcommon.o
+ ssb-y += driver_chipcommon_pmu.o
++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
+ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
+ ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
+ ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
+ ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
++ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
+
+ # b43 pci-ssb-bridge driver
+ # Not strictly a part of SSB, but kept here for convenience
+--- a/drivers/ssb/b43_pci_bridge.c
++++ b/drivers/ssb/b43_pci_bridge.c
+@@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
+ { 0, },
+ };
+ MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -4,6 +4,7 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+@@ -12,6 +13,7 @@
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/export.h>
+ #include <linux/pci.h>
++#include <linux/bcm47xx_wdt.h>
+
+ #include "ssb_private.h"
+
+@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
+ cc->fast_pwrup_delay = tmp;
+ }
+
++static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
++{
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_alp_clock(cc);
++
++ return 20000000;
++}
++
++static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
++{
++ u32 nb;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (cc->dev->id.revision < 26)
++ nb = 16;
++ else
++ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ return ssb_chipco_watchdog_timer_set(cc, ticks);
++}
++
++u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ if (cc->dev->id.revision < 18)
++ return ssb_clockspeed(bus) / 1000;
++ else
++ return ssb_chipco_alp_clock(cc) / 1000;
++ }
++}
++
+ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+ return; /* We don't have a ChipCommon */
++
++ spin_lock_init(&cc->gpio_lock);
++
+ if (cc->dev->id.revision >= 11)
+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
+@@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ calc_fast_powerup_delay(cc);
++
++ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
++ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
++ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++ }
+ }
+
+ void ssb_chipco_suspend(struct ssb_chipcommon *cc)
+@@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
++u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
+ {
+- /* instant NMI */
+- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ u32 maxt;
++ enum ssb_clkmode clkmode;
++
++ maxt = ssb_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
++ ssb_chipco_set_clockmode(cc, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+@@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
+
+ u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+ EXPORT_SYMBOL(ssb_chipco_gpio_control);
+
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res = 0;
++
++ if (cc->dev->id.revision < 20)
++ return 0xffffffff;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res = 0;
++
++ if (cc->dev->id.revision < 20)
++ return 0xffffffff;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ #ifdef CONFIG_SSB_SERIAL
+@@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
+ } else if ((ccrev >= 11) && (ccrev != 15)) {
+- /* Fixed ALP clock */
+- baud_base = 20000000;
+- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
+- /* FIXME: baud_base is different for devices with a PMU */
+- SSB_WARN_ON(1);
+- }
++ baud_base = ssb_chipco_alp_clock(cc);
+ div = 1;
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -13,6 +13,9 @@
+ #include <linux/ssb/ssb_driver_chipcommon.h>
+ #include <linux/delay.h>
+ #include <linux/export.h>
++#ifdef CONFIG_BCM47XX
++#include <asm/mach-bcm47xx/nvram.h>
++#endif
+
+ #include "ssb_private.h"
+
+@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
+ u32 pmuctl, tmp, pllctl;
+ unsigned int i;
+
+- if ((bus->chip_id == 0x5354) && !crystalfreq) {
+- /* The 5354 crystal freq is 25MHz */
+- crystalfreq = 25000;
+- }
+ if (crystalfreq)
+ e = pmu0_plltab_find_entry(crystalfreq);
+ if (!e)
+@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
+ u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
+
+ if (bus->bustype == SSB_BUSTYPE_SSB) {
+- /* TODO: The user may override the crystal frequency. */
++#ifdef CONFIG_BCM47XX
++ char buf[20];
++ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
++ crystalfreq = simple_strtoul(buf, NULL, 0);
++#endif
+ }
+
+ switch (bus->chip_id) {
+@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
+ ssb_pmu1_pllinit_r0(cc, crystalfreq);
+ break;
+ case 0x4328:
++ ssb_pmu0_pllinit_r0(cc, crystalfreq);
++ break;
+ case 0x5354:
++ if (crystalfreq == 0)
++ crystalfreq = 25000;
+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ break;
+ case 0x4322:
+@@ -339,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
+ }
+ break;
++ case 43222:
++ break;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PLL init unknown for device %04X\n",
+@@ -427,6 +436,7 @@ static void ssb_pmu_resources_init(struc
+ min_msk = 0xCBB;
+ break;
+ case 0x4322:
++ case 43222:
+ /* We keep the default settings:
+ * min_msk = 0xCBB
+ * max_msk = 0x7FFFF
+@@ -607,3 +617,61 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
++
++static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
++{
++ u32 crystalfreq;
++ const struct pmu0_plltab_entry *e = NULL;
++
++ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
++ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
++ e = pmu0_plltab_find_entry(crystalfreq);
++ BUG_ON(!e);
++ return e->freq * 1000;
++}
++
++u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ ssb_pmu_get_alp_clock_clk0(cc);
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU alp clock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
++
++u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
++ return 240000000;
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU cpu clock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
++
++u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ return 120000000;
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU controlclock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
+--- /dev/null
++++ b/drivers/ssb/driver_chipcommon_sflash.c
+@@ -0,0 +1,18 @@
++/*
++ * Sonics Silicon Backplane
++ * ChipCommon serial flash interface
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/ssb/ssb.h>
++
++#include "ssb_private.h"
++
++/* Initialize serial flash access */
++int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ pr_err("Serial flash support is not implemented yet!\n");
++
++ return -ENOTSUPP;
++}
+--- a/drivers/ssb/driver_extif.c
++++ b/drivers/ssb/driver_extif.c
+@@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
+ *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
+ {
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++
++ return ssb_extif_watchdog_timer_set(extif, ticks);
++}
++
++u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
++
++ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
++
++ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
++}
++
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
++ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
+ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
++
++ return ticks;
++}
++
++void ssb_extif_init(struct ssb_extif *extif)
++{
++ if (!extif->dev)
++ return; /* We don't have a Extif core */
++ spin_lock_init(&extif->gpio_lock);
+ }
+
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
+@@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
+
+ u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
+ mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
+ mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+--- /dev/null
++++ b/drivers/ssb/driver_gpio.c
+@@ -0,0 +1,176 @@
++/*
++ * Sonics Silicon Backplane
++ * GPIO driver
++ *
++ * Copyright 2011, Broadcom Corporation
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/gpio.h>
++#include <linux/export.h>
++#include <linux/ssb/ssb.h>
++
++#include "ssb_private.h"
++
++static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
++{
++ return container_of(chip, struct ssb_bus, gpio);
++}
++
++static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
++}
++
++static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
++}
++
++static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
++ unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
++ return 0;
++}
++
++static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
++ unsigned gpio, int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
++ return 0;
++}
++
++static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
++ /* clear pulldown */
++ ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
++ /* Set pullup */
++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
++
++ return 0;
++}
++
++static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ /* clear pullup */
++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
++}
++
++static int ssb_gpio_chipco_init(struct ssb_bus *bus)
++{
++ struct gpio_chip *chip = &bus->gpio;
++
++ chip->label = "ssb_chipco_gpio";
++ chip->owner = THIS_MODULE;
++ chip->request = ssb_gpio_chipco_request;
++ chip->free = ssb_gpio_chipco_free;
++ chip->get = ssb_gpio_chipco_get_value;
++ chip->set = ssb_gpio_chipco_set_value;
++ chip->direction_input = ssb_gpio_chipco_direction_input;
++ chip->direction_output = ssb_gpio_chipco_direction_output;
++ chip->ngpio = 16;
++ /* There is just one SoC in one device and its GPIO addresses should be
++ * deterministic to address them more easily. The other buses could get
++ * a random base number. */
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ chip->base = 0;
++ else
++ chip->base = -1;
++
++ return gpiochip_add(chip);
++}
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++
++static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
++}
++
++static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
++}
++
++static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
++ unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
++ return 0;
++}
++
++static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
++ unsigned gpio, int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
++ return 0;
++}
++
++static int ssb_gpio_extif_init(struct ssb_bus *bus)
++{
++ struct gpio_chip *chip = &bus->gpio;
++
++ chip->label = "ssb_extif_gpio";
++ chip->owner = THIS_MODULE;
++ chip->get = ssb_gpio_extif_get_value;
++ chip->set = ssb_gpio_extif_set_value;
++ chip->direction_input = ssb_gpio_extif_direction_input;
++ chip->direction_output = ssb_gpio_extif_direction_output;
++ chip->ngpio = 5;
++ /* There is just one SoC in one device and its GPIO addresses should be
++ * deterministic to address them more easily. The other buses could get
++ * a random base number. */
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ chip->base = 0;
++ else
++ chip->base = -1;
++
++ return gpiochip_add(chip);
++}
++
++#else
++static int ssb_gpio_extif_init(struct ssb_bus *bus)
++{
++ return -ENOTSUPP;
++}
++#endif
++
++int ssb_gpio_init(struct ssb_bus *bus)
++{
++ if (ssb_chipco_available(&bus->chipco))
++ return ssb_gpio_chipco_init(bus);
++ else if (ssb_extif_available(&bus->extif))
++ return ssb_gpio_extif_init(bus);
++ else
++ SSB_WARN_ON(1);
++
++ return -1;
++}
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+ else
+ mcore->nr_serial_ports = 0;
+@@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
+
+- mcore->flash_buswidth = 2;
+- if (bus->chipco.dev) {
+- mcore->flash_window = 0x1c000000;
+- mcore->flash_window_size = 0x02000000;
++ /* When there is no chipcommon on the bus there is 4MB flash */
++ if (!ssb_chipco_available(&bus->chipco)) {
++ mcore->pflash.present = true;
++ mcore->pflash.buswidth = 2;
++ mcore->pflash.window = SSB_FLASH1;
++ mcore->pflash.window_size = SSB_FLASH1_SZ;
++ return;
++ }
++
++ /* There is ChipCommon, so use it to read info about flash */
++ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
++ case SSB_CHIPCO_FLASHT_STSER:
++ case SSB_CHIPCO_FLASHT_ATSER:
++ pr_debug("Found serial flash\n");
++ ssb_sflash_init(&bus->chipco);
++ break;
++ case SSB_CHIPCO_FLASHT_PARA:
++ pr_debug("Found parallel flash\n");
++ mcore->pflash.present = true;
++ mcore->pflash.window = SSB_FLASH2;
++ mcore->pflash.window_size = SSB_FLASH2_SZ;
+ if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
+ & SSB_CHIPCO_CFG_DS16) == 0)
+- mcore->flash_buswidth = 1;
+- } else {
+- mcore->flash_window = 0x1fc00000;
+- mcore->flash_window_size = 0x00400000;
++ mcore->pflash.buswidth = 1;
++ else
++ mcore->pflash.buswidth = 2;
++ break;
+ }
+ }
+
+@@ -208,9 +225,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+ struct ssb_bus *bus = mcore->dev->bus;
+ u32 pll_type, n, m, rate = 0;
+
+- if (bus->extif.dev) {
++ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_cpu_clock(&bus->chipco);
++
++ if (ssb_extif_available(&bus->extif)) {
+ ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
+- } else if (bus->chipco.dev) {
++ } else if (ssb_chipco_available(&bus->chipco)) {
+ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
+ } else
+ return 0;
+@@ -246,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+ hz = 100000000;
+ ns = 1000000000 / hz;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ ssb_extif_timing_init(&bus->extif, ns);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ ssb_chipco_timing_init(&bus->chipco, ns);
+
+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -4,11 +4,13 @@
+ *
+ * Copyright 2005-2008, Broadcom Corporation
+ * Copyright 2006-2008, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/ssb/ssb_driver_pci.h>
+@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ if (ssb_chipco_available(&bus->chipco)) {
++ wdt.driver_data = &bus->chipco;
++ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
++ wdt.max_timer_ms = bus->chipco.max_timer_ms;
++ } else if (ssb_extif_available(&bus->extif)) {
++ wdt.driver_data = &bus->extif;
++ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
++ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
++ } else {
++ return -ENODEV;
++ }
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ bus->busnumber, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev)) {
++ ssb_dprintk(KERN_INFO PFX
++ "can not register watchdog device, err: %li\n",
++ PTR_ERR(pdev));
++ return PTR_ERR(pdev);
++ }
++
++ bus->watchdog = pdev;
++ return 0;
++}
++
+ u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
+ {
+ unsigned long flags;
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -13,6 +13,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/ssb/ssb_driver_gige.h>
+@@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
+ put_device(dev->dev);
+ }
+
+-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
+-{
+- if (drv)
+- get_driver(&drv->drv);
+- return drv;
+-}
+-
+-static inline void ssb_driver_put(struct ssb_driver *drv)
+-{
+- if (drv)
+- put_driver(&drv->drv);
+-}
+-
+ static int ssb_device_resume(struct device *dev)
+ {
+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+@@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
+ ssb_device_put(sdev);
+ continue;
+ }
+- sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
+- if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
+- ssb_device_put(sdev);
++ sdrv = drv_to_ssb_drv(sdev->dev->driver);
++ if (SSB_WARN_ON(!sdrv->remove))
+ continue;
+- }
+ sdrv->remove(sdev);
+ ctx->device_frozen[i] = 1;
+ }
+@@ -293,7 +279,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
+ dev_name(sdev->dev));
+ result = err;
+ }
+- ssb_driver_put(sdrv);
+ ssb_device_put(sdev);
+ }
+
+@@ -449,6 +434,11 @@ static void ssb_devices_unregister(struc
+ if (sdev->dev)
+ device_unregister(sdev->dev);
+ }
++
++#ifdef CONFIG_SSB_EMBEDDED
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ platform_device_unregister(bus->watchdog);
++#endif
+ }
+
+ void ssb_bus_unregister(struct ssb_bus *bus)
+@@ -577,6 +567,8 @@ static int __devinit ssb_attach_queued_b
+ if (err)
+ goto error;
+ ssb_pcicore_init(&bus->pcicore);
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ ssb_watchdog_register(bus);
+ ssb_bus_may_powerdown(bus);
+
+ err = ssb_devices_register(bus);
+@@ -812,7 +804,14 @@ static int __devinit ssb_bus_register(st
+ if (err)
+ goto err_pcmcia_exit;
+ ssb_chipcommon_init(&bus->chipco);
++ ssb_extif_init(&bus->extif);
+ ssb_mipscore_init(&bus->mipscore);
++ err = ssb_gpio_init(bus);
++ if (err == -ENOTSUPP)
++ ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
++ else if (err)
++ ssb_dprintk(KERN_ERR PFX
++ "Error registering GPIO driver: %i\n", err);
+ err = ssb_fetch_invariants(bus, get_invariants);
+ if (err) {
+ ssb_bus_may_powerdown(bus);
+@@ -1094,6 +1093,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+ u32 plltype;
+ u32 clkctl_n, clkctl_m;
+
++ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_controlclock(&bus->chipco);
++
+ if (ssb_extif_available(&bus->extif))
+ ssb_extif_get_clockcontrol(&bus->extif, &plltype,
+ &clkctl_n, &clkctl_m);
+@@ -1131,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
+ default:
+- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+- WARN_ON(1);
++ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }
+ return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
+ }
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
-@@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
+@@ -178,6 +178,18 @@ err_pci:
+ #define SPEX(_outvar, _offset, _mask, _shift) \
+ SPEX16(_outvar, _offset, _mask, _shift)
+
++#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
++ do { \
++ SPEX(_field[0], _offset + 0, _mask, _shift); \
++ SPEX(_field[1], _offset + 2, _mask, _shift); \
++ SPEX(_field[2], _offset + 4, _mask, _shift); \
++ SPEX(_field[3], _offset + 6, _mask, _shift); \
++ SPEX(_field[4], _offset + 8, _mask, _shift); \
++ SPEX(_field[5], _offset + 10, _mask, _shift); \
++ SPEX(_field[6], _offset + 12, _mask, _shift); \
++ SPEX(_field[7], _offset + 14, _mask, _shift); \
++ } while (0)
++
+
+ static inline u8 ssb_crc8(u8 crc, u8 data)
+ {
+@@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
+ {
+ int i;
+ u16 v;
+- s8 gain;
+ u16 loc[3];
+
+ if (out->revision == 3) /* rev 3 moved MAC */
+@@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
+ SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
+ SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
+ SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
+- SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
+- SSB_SPROM1_BINF_CCODE_SHIFT);
++ if (out->revision == 1)
++ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
++ SSB_SPROM1_BINF_CCODE_SHIFT);
+ SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
+ SSB_SPROM1_BINF_ANTA_SHIFT);
+ SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
+@@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
+ SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
+ if (out->revision >= 2)
+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
++ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
++ SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
+
+ /* Extract the antenna gain values. */
+- gain = r123_extract_antgain(out->revision, in,
+- SSB_SPROM1_AGAIN_BG,
+- SSB_SPROM1_AGAIN_BG_SHIFT);
+- out->antenna_gain.ghz24.a0 = gain;
+- out->antenna_gain.ghz24.a1 = gain;
+- out->antenna_gain.ghz24.a2 = gain;
+- out->antenna_gain.ghz24.a3 = gain;
+- gain = r123_extract_antgain(out->revision, in,
+- SSB_SPROM1_AGAIN_A,
+- SSB_SPROM1_AGAIN_A_SHIFT);
+- out->antenna_gain.ghz5.a0 = gain;
+- out->antenna_gain.ghz5.a1 = gain;
+- out->antenna_gain.ghz5.a2 = gain;
+- out->antenna_gain.ghz5.a3 = gain;
++ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
++ SSB_SPROM1_AGAIN_BG,
++ SSB_SPROM1_AGAIN_BG_SHIFT);
++ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
++ SSB_SPROM1_AGAIN_A,
++ SSB_SPROM1_AGAIN_A_SHIFT);
+ }
+
+ /* Revs 4 5 and 8 have partially shared layout */
+@@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
+ SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
+ SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
+ SSB_SPROM4_ETHPHY_ET1A_SHIFT);
++ SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
+ if (out->revision == 4) {
+- SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
++ SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
++ SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
+ SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
+ SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
+ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
+ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
+ } else {
+- SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
++ SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
++ SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
+ SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
+ SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
+ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
+@@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
+ }
+
+ /* Extract the antenna gain values. */
+- SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
++ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
+ SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
+- SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
++ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
+ SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
+- SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
++ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
+ SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
+- SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
++ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
+ SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
+- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
+- sizeof(out->antenna_gain.ghz5));
+
+ sprom_extract_r458(out, in);
+
+@@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
{
int i;
/* extract the MAC address */
for (i = 0; i < 3; i++) {
-@@ -607,6 +613,38 @@ static void sprom_extract_r8(struct ssb_
- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- sizeof(out->antenna_gain.ghz5));
+ v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
+ *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
+ }
+- SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
++ SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
++ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
++ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
+ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
+ SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
+ SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
+@@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
+ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
+ /* Extract the antenna gain values. */
+- SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
++ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
+ SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
+- SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
++ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
+ SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
+- SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
++ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
+ SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
+- SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
++ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
+ SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
+- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
+- sizeof(out->antenna_gain.ghz5));
++
+ /* Extract cores power info info */
+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
+ o = pwr_info_offset[i];
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
+ }
-+
+
/* Extract FEM info */
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
- SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
+@@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
+
++ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
++ SSB_SPROM8_LEDDC_ON_SHIFT);
++ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
++ SSB_SPROM8_LEDDC_OFF_SHIFT);
++
++ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
++ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
++ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
++ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
++ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
++ SSB_SPROM8_TXRXC_SWITCH_SHIFT);
++
++ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
++
++ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
++ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
++ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
++ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
++
++ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
++ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
++ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
++ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
++ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
++ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
++ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
++ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
++ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
++ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
++ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
++ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
++
++ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
++ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
++ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
++ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
++
++ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
++ SSB_SPROM8_THERMAL_TRESH_SHIFT);
++ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
++ SSB_SPROM8_THERMAL_OFFSET_SHIFT);
++ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
++ SSB_SPROM8_TEMPDELTA_PHYCAL,
++ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
++ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
++ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
++ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
++ SSB_SPROM8_TEMPDELTA_HYSTERESIS,
++ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
+ sprom_extract_r458(out, in);
+
+ /* TODO - get remaining rev 8 stuff needed */
+@@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
+ {
+ bi->vendor = bus->host_pci->subsystem_vendor;
+ bi->type = bus->host_pci->subsystem_device;
+- bi->rev = bus->host_pci->revision;
+ }
+
+ int ssb_pci_get_invariants(struct ssb_bus *bus,
+--- a/drivers/ssb/pcmcia.c
++++ b/drivers/ssb/pcmcia.c
+@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
+ case SSB_PCMCIA_CIS_ANTGAIN:
+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
+ "antg tpl size");
+- sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
+- sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
++ sprom->antenna_gain.a0 = tuple->TupleData[1];
++ sprom->antenna_gain.a1 = tuple->TupleData[1];
++ sprom->antenna_gain.a2 = tuple->TupleData[1];
++ sprom->antenna_gain.a3 = tuple->TupleData[1];
+ break;
+ case SSB_PCMCIA_CIS_BFLAGS:
+ GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
+--- a/drivers/ssb/scan.c
++++ b/drivers/ssb/scan.c
+@@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
+ return "ARM 1176";
+ case SSB_DEV_ARM_7TDMI:
+ return "ARM 7TDMI";
++ case SSB_DEV_ARM_CM3:
++ return "ARM Cortex M3";
+ }
+ return "UNKNOWN";
+ }
+@@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ bus->chip_package = 0;
+ }
+ }
++ ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
++ "package 0x%02X\n", bus->chip_id, bus->chip_rev,
++ bus->chip_package);
+ if (!bus->nr_devices)
+ bus->nr_devices = chipid_to_nrcores(bus->chip_id);
+ if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
+--- a/drivers/ssb/sdio.c
++++ b/drivers/ssb/sdio.c
+@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
+ case SSB_SDIO_CIS_ANTGAIN:
+ GOTO_ERROR_ON(tuple->size != 2,
+ "antg tpl size");
+- sprom->antenna_gain.ghz24.a0 = tuple->data[1];
+- sprom->antenna_gain.ghz24.a1 = tuple->data[1];
+- sprom->antenna_gain.ghz24.a2 = tuple->data[1];
+- sprom->antenna_gain.ghz24.a3 = tuple->data[1];
+- sprom->antenna_gain.ghz5.a0 = tuple->data[1];
+- sprom->antenna_gain.ghz5.a1 = tuple->data[1];
+- sprom->antenna_gain.ghz5.a2 = tuple->data[1];
+- sprom->antenna_gain.ghz5.a3 = tuple->data[1];
++ sprom->antenna_gain.a0 = tuple->data[1];
++ sprom->antenna_gain.a1 = tuple->data[1];
++ sprom->antenna_gain.a2 = tuple->data[1];
++ sprom->antenna_gain.a3 = tuple->data[1];
+ break;
+ case SSB_SDIO_CIS_BFLAGS:
+ GOTO_ERROR_ON((tuple->size != 3) &&
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -3,6 +3,7 @@
+
+ #include <linux/ssb/ssb.h>
+ #include <linux/types.h>
++#include <linux/bcm47xx_wdt.h>
+
+
+ #define PFX "ssb: "
+@@ -207,4 +208,66 @@ static inline void b43_pci_ssb_bridge_ex
+ }
+ #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+
++/* driver_chipcommon_pmu.c */
++extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
++
++extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++
++/* driver_chipcommon_sflash.c */
++#ifdef CONFIG_SSB_SFLASH
++int ssb_sflash_init(struct ssb_chipcommon *cc);
++#else
++static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ pr_err("Serial flash not supported\n");
++ return 0;
++}
++#endif /* CONFIG_SSB_SFLASH */
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++#else
++static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ return 0;
++}
++static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_SSB_EMBEDDED
++extern int ssb_watchdog_register(struct ssb_bus *bus);
++#else /* CONFIG_SSB_EMBEDDED */
++static inline int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_EMBEDDED */
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern void ssb_extif_init(struct ssb_extif *extif);
++#else
++static inline void ssb_extif_init(struct ssb_extif *extif)
++{
++}
++#endif
++
++#ifdef CONFIG_SSB_DRIVER_GPIO
++extern int ssb_gpio_init(struct ssb_bus *bus);
++#else /* CONFIG_SSB_DRIVER_GPIO */
++static inline int ssb_gpio_init(struct ssb_bus *bus)
++{
++ return -ENOTSUPP;
++}
++#endif /* CONFIG_SSB_DRIVER_GPIO */
++
+ #endif /* LINUX_SSB_PRIVATE_H_ */
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
-@@ -16,6 +16,12 @@ struct pcmcia_device;
+@@ -6,8 +6,10 @@
+ #include <linux/types.h>
+ #include <linux/spinlock.h>
+ #include <linux/pci.h>
++#include <linux/gpio.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
+
+ #include <linux/ssb/ssb_regs.h>
+
+@@ -16,6 +18,12 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
+struct ssb_sprom_core_pwr_info {
+ u8 itssi_2g, itssi_5g;
+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
-+ u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
++ u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
+};
+
struct ssb_sprom {
u8 revision;
u8 il0mac[6]; /* MAC address for 802.11b/g */
-@@ -82,6 +88,8 @@ struct ssb_sprom {
+@@ -26,9 +34,12 @@ struct ssb_sprom {
+ u8 et0mdcport; /* MDIO for enet0 */
+ u8 et1mdcport; /* MDIO for enet1 */
+ u16 board_rev; /* Board revision number from SPROM. */
++ u16 board_num; /* Board number from SPROM. */
++ u16 board_type; /* Board type from SPROM. */
+ u8 country_code; /* Country Code */
+- u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
+- u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
++ char alpha2[2]; /* Country Code as two chars like EU or US */
++ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
++ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
+ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
+ u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
+ u16 pa0b0;
+@@ -47,10 +58,10 @@ struct ssb_sprom {
+ u8 gpio1; /* GPIO pin 1 */
+ u8 gpio2; /* GPIO pin 2 */
+ u8 gpio3; /* GPIO pin 3 */
+- u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
+- u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
+- u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
+- u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
++ u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
++ u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
++ u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
++ u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
+ u8 itssi_a; /* Idle TSSI Target for A-PHY */
+ u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
+ u8 tri2g; /* 2.4GHz TX isolation */
+@@ -61,8 +72,8 @@ struct ssb_sprom {
+ u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
+ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
+ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
+- u8 rxpo2g; /* 2GHz RX power offset */
+- u8 rxpo5g; /* 5GHz RX power offset */
++ s8 rxpo2g; /* 2GHz RX power offset */
++ s8 rxpo5g; /* 5GHz RX power offset */
+ u8 rssisav2g; /* 2GHz RSSI params */
+ u8 rssismc2g;
+ u8 rssismf2g;
+@@ -82,16 +93,13 @@ struct ssb_sprom {
u16 boardflags2_hi; /* Board flags (bits 48-63) */
/* TODO store board flags in a single u64 */
/* Antenna gain values for up to 4 antennas
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
* loss in the connectors is bigger than the gain. */
+ struct {
+- struct {
+- s8 a0, a1, a2, a3;
+- } ghz24; /* 2.4GHz band */
+- struct {
+- s8 a0, a1, a2, a3;
+- } ghz5; /* 5GHz band */
++ s8 a0, a1, a2, a3;
+ } antenna_gain;
+
+ struct {
+@@ -103,14 +111,85 @@ struct ssb_sprom {
+ } ghz5;
+ } fem;
+
+- /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
++ u16 mcs2gpo[8];
++ u16 mcs5gpo[8];
++ u16 mcs5glpo[8];
++ u16 mcs5ghpo[8];
++ u8 opo;
++
++ u8 rxgainerr2ga[3];
++ u8 rxgainerr5gla[3];
++ u8 rxgainerr5gma[3];
++ u8 rxgainerr5gha[3];
++ u8 rxgainerr5gua[3];
++
++ u8 noiselvl2ga[3];
++ u8 noiselvl5gla[3];
++ u8 noiselvl5gma[3];
++ u8 noiselvl5gha[3];
++ u8 noiselvl5gua[3];
++
++ u8 regrev;
++ u8 txchain;
++ u8 rxchain;
++ u8 antswitch;
++ u16 cddpo;
++ u16 stbcpo;
++ u16 bw40po;
++ u16 bwduppo;
++
++ u8 tempthresh;
++ u8 tempoffset;
++ u16 rawtempsense;
++ u8 measpower;
++ u8 tempsense_slope;
++ u8 tempcorrx;
++ u8 tempsense_option;
++ u8 freqoffset_corr;
++ u8 iqcal_swp_dis;
++ u8 hw_iqcal_en;
++ u8 elna2g;
++ u8 elna5g;
++ u8 phycal_tempdelta;
++ u8 temps_period;
++ u8 temps_hysteresis;
++ u8 measpower1;
++ u8 measpower2;
++ u8 pcieingress_war;
++
++ /* power per rate from sromrev 9 */
++ u16 cckbw202gpo;
++ u16 cckbw20ul2gpo;
++ u32 legofdmbw202gpo;
++ u32 legofdmbw20ul2gpo;
++ u32 legofdmbw205glpo;
++ u32 legofdmbw20ul5glpo;
++ u32 legofdmbw205gmpo;
++ u32 legofdmbw20ul5gmpo;
++ u32 legofdmbw205ghpo;
++ u32 legofdmbw20ul5ghpo;
++ u32 mcsbw202gpo;
++ u32 mcsbw20ul2gpo;
++ u32 mcsbw402gpo;
++ u32 mcsbw205glpo;
++ u32 mcsbw20ul5glpo;
++ u32 mcsbw405glpo;
++ u32 mcsbw205gmpo;
++ u32 mcsbw20ul5gmpo;
++ u32 mcsbw405gmpo;
++ u32 mcsbw205ghpo;
++ u32 mcsbw20ul5ghpo;
++ u32 mcsbw405ghpo;
++ u16 mcs32po;
++ u16 legofdm40duppo;
++ u8 sar2g;
++ u8 sar5g;
+ };
+
+ /* Information about the PCB the circuitry is soldered on. */
+ struct ssb_boardinfo {
+ u16 vendor;
+ u16 type;
+- u8 rev;
+ };
+
+
+@@ -166,6 +245,7 @@ struct ssb_bus_ops {
+ #define SSB_DEV_MINI_MACPHY 0x823
+ #define SSB_DEV_ARM_1176 0x824
+ #define SSB_DEV_ARM_7TDMI 0x825
++#define SSB_DEV_ARM_CM3 0x82A
+
+ /* Vendor-ID values */
+ #define SSB_VENDOR_BROADCOM 0x4243
+@@ -354,7 +434,11 @@ struct ssb_bus {
+ #ifdef CONFIG_SSB_EMBEDDED
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
++ struct platform_device *watchdog;
+ #endif /* EMBEDDED */
++#ifdef CONFIG_SSB_DRIVER_GPIO
++ struct gpio_chip gpio;
++#endif /* DRIVER_GPIO */
+
+ /* Internal-only stuff follows. Do not touch. */
+ struct list_head list;
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -504,7 +504,9 @@
+ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
+ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
+ #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
+-#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
++#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
++#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
++#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
+
+ /* Status register bits for ST flashes */
+ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
+@@ -588,7 +590,10 @@ struct ssb_chipcommon {
+ u32 status;
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
++ spinlock_t gpio_lock;
+ struct ssb_chipcommon_pmu pmu;
++ u32 ticks_per_ms;
++ u32 max_timer_ms;
+ };
+
+ static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
+@@ -628,8 +633,7 @@ enum ssb_clkmode {
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ enum ssb_clkmode mode);
+
+-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
+- u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
+ u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+ u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+ #ifdef CONFIG_SSB_SERIAL
+ extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+--- a/include/linux/ssb/ssb_driver_extif.h
++++ b/include/linux/ssb/ssb_driver_extif.h
+@@ -152,12 +152,16 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
+
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
++ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
+
+
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+
+ struct ssb_extif {
+ struct ssb_device *dev;
++ spinlock_t gpio_lock;
+ };
+
+ static inline bool ssb_extif_available(struct ssb_extif *extif)
+@@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
+ extern void ssb_extif_timing_init(struct ssb_extif *extif,
+ unsigned long ns);
+
+-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
+
+ /* Extif GPIO pin access */
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
+@@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
+ }
+
+ static inline
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
+ {
+ }
+
++static inline
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++#ifdef CONFIG_SSB_SERIAL
++static inline int ssb_extif_serial_init(struct ssb_extif *extif,
++ struct ssb_serial_port *ports)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_SERIAL */
++
+ #endif /* CONFIG_SSB_DRIVER_EXTIF */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
+--- a/include/linux/ssb/ssb_driver_gige.h
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -2,6 +2,7 @@
+ #define LINUX_SSB_DRIVER_GIGE_H_
+
+ #include <linux/ssb/ssb.h>
++#include <linux/bug.h>
+ #include <linux/pci.h>
+ #include <linux/spinlock.h>
+
+--- a/include/linux/ssb/ssb_driver_mips.h
++++ b/include/linux/ssb/ssb_driver_mips.h
+@@ -13,6 +13,12 @@ struct ssb_serial_port {
+ unsigned int reg_shift;
+ };
+
++struct ssb_pflash {
++ bool present;
++ u8 buswidth;
++ u32 window;
++ u32 window_size;
++};
+
+ struct ssb_mipscore {
+ struct ssb_device *dev;
+@@ -20,9 +26,7 @@ struct ssb_mipscore {
+ int nr_serial_ports;
+ struct ssb_serial_port serial_ports[4];
+
+- u8 flash_buswidth;
+- u32 flash_window;
+- u32 flash_window_size;
++ struct ssb_pflash pflash;
+ };
+
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
-@@ -449,6 +449,39 @@
- #define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
- #define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
- #define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
+@@ -228,6 +228,7 @@
+ #define SSB_SPROM1_AGAIN_BG_SHIFT 0
+ #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
+ #define SSB_SPROM1_AGAIN_A_SHIFT 8
++#define SSB_SPROM1_CCODE 0x0076
+
+ /* SPROM Revision 2 (inherits from rev 1) */
+ #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
+@@ -267,6 +268,7 @@
+ #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+
+ /* SPROM Revision 4 */
++#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
+ #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
+ #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
+ #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
+@@ -389,6 +391,11 @@
+ #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
+ #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
+ #define SSB_SPROM8_GPIOB_P3_SHIFT 8
++#define SSB_SPROM8_LEDDC 0x009A
++#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
++#define SSB_SPROM8_LEDDC_ON_SHIFT 8
++#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
++#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
+ #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
+ #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
+ #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
+@@ -404,6 +411,13 @@
+ #define SSB_SPROM8_AGAIN2_SHIFT 0
+ #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
+ #define SSB_SPROM8_AGAIN3_SHIFT 8
++#define SSB_SPROM8_TXRXC 0x00A2
++#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
++#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
++#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
++#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
++#define SSB_SPROM8_TXRXC_SWITCH 0xff00
++#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
+ #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
+ #define SSB_SPROM8_RSSISMF2G 0x000F
+ #define SSB_SPROM8_RSSISMC2G 0x00F0
+@@ -430,6 +444,7 @@
+ #define SSB_SPROM8_TRI5GH_SHIFT 8
+ #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
+ #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
++#define SSB_SPROM8_RXPO2G_SHIFT 0
+ #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
+ #define SSB_SPROM8_RXPO5G_SHIFT 8
+ #define SSB_SPROM8_FEM2G 0x00AE
+@@ -445,10 +460,71 @@
+ #define SSB_SROM8_FEM_ANTSWLUT 0xF800
+ #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
+ #define SSB_SPROM8_THERMAL 0x00B2
+-#define SSB_SPROM8_MPWR_RAWTS 0x00B4
+-#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
+-#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
+-#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
++#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
++#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
++#define SSB_SPROM8_THERMAL_TRESH 0xff00
++#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
++/* Temp sense related entries */
++#define SSB_SPROM8_RAWTS 0x00B4
++#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
++#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
++#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
++#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
++#define SSB_SPROM8_OPT_CORRX 0x00B6
++#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
++#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
++#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
++#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
++#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
++#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
++/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
++#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
++#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
++#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
++#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
++#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
++#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
++#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
++#define SSB_SPROM8_TEMPDELTA 0x00BC
++#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
++#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
++#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
++#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
++#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
++#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
+
+/* There are 4 blocks with power info sharing the same layout */
+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
-@@ -473,6 +506,7 @@
+@@ -473,12 +549,23 @@
#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
#define SSB_SPROM8_PA1HIB1 0x00DA
#define SSB_SPROM8_PA1HIB2 0x00DC
#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
+ #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
+ #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
+
++#define SSB_SPROM8_2G_MCSPO 0x0152
++#define SSB_SPROM8_5G_MCSPO 0x0162
++#define SSB_SPROM8_5GL_MCSPO 0x0172
++#define SSB_SPROM8_5GH_MCSPO 0x0182
++
++#define SSB_SPROM8_CDDPO 0x0192
++#define SSB_SPROM8_STBCPO 0x0194
++#define SSB_SPROM8_BW40PO 0x0196
++#define SSB_SPROM8_BWDUPPO 0x0198
++
+ /* Values for boardflags_lo read from SPROM */
+ #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
+ #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
+--- /dev/null
++++ b/include/linux/bcm47xx_wdt.h
+@@ -0,0 +1,19 @@
++#ifndef LINUX_BCM47XX_WDT_H_
++#define LINUX_BCM47XX_WDT_H_
++
++#include <linux/types.h>
++
++
++struct bcm47xx_wdt {
++ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
++ u32 max_timer_ms;
++
++ void *driver_data;
++};
++
++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
++{
++ return wdt->driver_data;
++}
++#endif /* LINUX_BCM47XX_WDT_H_ */
projects / oweals / openwrt.git / blobdiff