cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
-@@ -205,6 +240,7 @@ static inline void protected_flush_icach
+@@ -205,6 +240,7 @@ static inline int protected_flush_icache
#ifdef CONFIG_EVA
return protected_cachee_op(Hit_Invalidate_I, addr);
#else
return protected_cache_op(Hit_Invalidate_I, addr);
#endif
}
-@@ -218,6 +254,7 @@ static inline void protected_flush_icach
+@@ -218,6 +254,7 @@ static inline int protected_flush_icache
*/
static inline int protected_writeback_dcache_line(unsigned long addr)
{
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -952,6 +964,8 @@ static void local_r4k_flush_cache_sigtra
+@@ -955,6 +967,8 @@ static void local_r4k_flush_cache_sigtra
}
R4600_HIT_CACHEOP_WAR_IMPL;
if (!cpu_has_ic_fills_f_dc) {
if (dc_lsize)
vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-@@ -1846,6 +1860,17 @@ static void coherency_setup(void)
+@@ -1849,6 +1863,17 @@ static void coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1892,6 +1917,15 @@ void r4k_cache_init(void)
+@@ -1895,6 +1920,15 @@ void r4k_cache_init(void)
extern void build_copy_page(void);
struct cpuinfo_mips *c = ¤t_cpu_data;
probe_pcache();
probe_vcache();
setup_scache();
-@@ -1969,7 +2003,15 @@ void r4k_cache_init(void)
+@@ -1972,7 +2006,15 @@ void r4k_cache_init(void)
*/
local_r4k___flush_cache_all(NULL);
/*
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -971,6 +971,9 @@ build_get_pgde32(u32 **p, unsigned int t
+@@ -971,6 +971,9 @@ void build_get_pgde32(u32 **p, unsigned
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
uasm_i_addu(p, ptr, tmp, ptr);
#else