ar71xx: ethernet: reduce tx dma ring size further to improve cache footprint

[librecmc/librecmc.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index ec764c5c2f4cb762e98dd4f8f4bea4182392eee9..606c6f1c057e8e3f3b2f3e3c0f503c4471edf66b 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -53,12 +53,13 @@
 #define AG71XX_TX_MTU_LEN      1540
 #define AG71XX_RX_PKT_SIZE     \
        (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
+#define AG71XX_RX_BUF_SIZE (AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN)
 
-#define AG71XX_TX_RING_SIZE_DEFAULT    64
+#define AG71XX_TX_RING_SIZE_DEFAULT    32
 #define AG71XX_RX_RING_SIZE_DEFAULT    128
 
-#define AG71XX_TX_RING_SIZE_MAX                256
-#define AG71XX_RX_RING_SIZE_MAX                256
+#define AG71XX_TX_RING_SIZE_MAX                32
+#define AG71XX_RX_RING_SIZE_MAX                128
 
 #ifdef CONFIG_AG71XX_DEBUG
 #define DBG(fmt, args...)      pr_debug(fmt, ## args)
@@ -85,10 +86,16 @@ struct ag71xx_desc {
 } __attribute__((aligned(4)));
 
 struct ag71xx_buf {
-       struct sk_buff          *skb;
+       union {
+               struct sk_buff  *skb;
+               void            *rx_buf;
+       };
        struct ag71xx_desc      *desc;
-       dma_addr_t              dma_addr;
-       unsigned long           timestamp;
+       union {
+               dma_addr_t      dma_addr;
+               unsigned long   timestamp;
+       };
+       unsigned int            len;
 };
 
 struct ag71xx_ring {
@@ -322,6 +329,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MII_CFG_CLK_DIV_14     5
 #define MII_CFG_CLK_DIV_20     6
 #define MII_CFG_CLK_DIV_28     7
+#define MII_CFG_CLK_DIV_34     8
+#define MII_CFG_CLK_DIV_42     9
+#define MII_CFG_CLK_DIV_50     10
+#define MII_CFG_CLK_DIV_58     11
+#define MII_CFG_CLK_DIV_66     12
+#define MII_CFG_CLK_DIV_74     13
+#define MII_CFG_CLK_DIV_82     14
+#define MII_CFG_CLK_DIV_98     15
 #define MII_CFG_RESET          BIT(31)
 
 #define MII_CMD_WRITE          0x0