ar71xx: build ALFA AP96 images with default profile as well

[oweals/openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 46346648fa36e787d1235f7d518d5d64fe7c0ad5..c391fee4a47b950bd9ea0656601afbed8e603ddc 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -79,6 +79,8 @@
 
 #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
 #define AR934X_WMAC_SIZE       0x20000
+#define AR934X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE       0x14
 
 #define AR71XX_MEM_SIZE_MIN    0x0200000
 #define AR71XX_MEM_SIZE_MAX    0x10000000
@@ -89,7 +91,9 @@
 #define AR71XX_GPIO_IRQ_BASE   40
 #define AR71XX_GPIO_IRQ_COUNT  32
 #define AR71XX_PCI_IRQ_BASE    72
-#define AR71XX_PCI_IRQ_COUNT   8
+#define AR71XX_PCI_IRQ_COUNT   6
+#define AR934X_IP2_IRQ_BASE    78
+#define AR934X_IP2_IRQ_COUNT   2
 
 #define AR71XX_CPU_IRQ_IP2     (AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_USB     (AR71XX_CPU_IRQ_BASE + 3)
@@ -119,6 +123,9 @@
 #define AR71XX_PCI_IRQ_DEV2    (AR71XX_PCI_IRQ_BASE + 2)
 #define AR71XX_PCI_IRQ_CORE    (AR71XX_PCI_IRQ_BASE + 4)
 
+#define AR934X_IP2_IRQ_WMAC    (AR934X_IP2_IRQ_BASE + 0)
+#define AR934X_IP2_IRQ_PCIE    (AR934X_IP2_IRQ_BASE + 1)
+
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
@@ -413,17 +420,25 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 /*
  * GPIO block
  */
-#define GPIO_REG_OE            0x00
-#define GPIO_REG_IN            0x04
-#define GPIO_REG_OUT           0x08
-#define GPIO_REG_SET           0x0c
-#define GPIO_REG_CLEAR         0x10
-#define GPIO_REG_INT_MODE      0x14
-#define GPIO_REG_INT_TYPE      0x18
-#define GPIO_REG_INT_POLARITY  0x1c
-#define GPIO_REG_INT_PENDING   0x20
-#define GPIO_REG_INT_ENABLE    0x24
-#define GPIO_REG_FUNC          0x28
+#define AR71XX_GPIO_REG_OE             0x00
+#define AR71XX_GPIO_REG_IN             0x04
+#define AR71XX_GPIO_REG_OUT            0x08
+#define AR71XX_GPIO_REG_SET            0x0c
+#define AR71XX_GPIO_REG_CLEAR          0x10
+#define AR71XX_GPIO_REG_INT_MODE       0x14
+#define AR71XX_GPIO_REG_INT_TYPE       0x18
+#define AR71XX_GPIO_REG_INT_POLARITY   0x1c
+#define AR71XX_GPIO_REG_INT_PENDING    0x20
+#define AR71XX_GPIO_REG_INT_ENABLE     0x24
+#define AR71XX_GPIO_REG_FUNC           0x28
+
+#define AR934X_GPIO_REG_OUT_FUNC0      0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1      0x30
+#define AR934X_GPIO_REG_OUT_FUNC2      0x34
+#define AR934X_GPIO_REG_OUT_FUNC3      0x38
+#define AR934X_GPIO_REG_OUT_FUNC4      0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5      0x40
+#define AR934X_GPIO_REG_FUNC           0x6c
 
 #define AR71XX_GPIO_FUNC_STEREO_EN     BIT(17)
 #define AR71XX_GPIO_FUNC_SLIC_EN       BIT(16)
@@ -453,7 +468,8 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 #define AR724X_GPIO_FUNC_UART_EN               BIT(1)
 #define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 
-#define AR724X_GPIO_COUNT      18
+#define AR7240_GPIO_COUNT      18
+#define AR7241_GPIO_COUNT      20
 
 #define AR91XX_GPIO_FUNC_WMAC_LED_EN   BIT(22)
 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN        BIT(21)
@@ -468,14 +484,36 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 
 #define AR91XX_GPIO_COUNT      22
 
+#define AR933X_GPIO_FUNC_SPDIF2TCK             BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN              BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN         BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN            BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN               BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL   BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL   BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT    BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN                        BIT(18)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN               BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
+
 #define AR933X_GPIO_COUNT      30
 
 #define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 #define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 
-#define AR934X_GPIO_COUNT              32
+#define AR934X_GPIO_COUNT              23
 #define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 
+#define AR934X_GPIO_OUT_GPIO           0x00
+
 extern void __iomem *ar71xx_gpio_base;
 
 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
@@ -492,6 +530,7 @@ void ar71xx_gpio_init(void) __init;
 void ar71xx_gpio_function_enable(u32 mask);
 void ar71xx_gpio_function_disable(u32 mask);
 void ar71xx_gpio_function_setup(u32 set, u32 clear);
+void ar71xx_gpio_output_select(unsigned gpio, u8 val);
 
 /*
  * DDR_CTRL block
@@ -528,6 +567,7 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear);
 #define AR934X_DDR_REG_FLUSH_GE1       0xa0
 #define AR934X_DDR_REG_FLUSH_USB       0xa4
 #define AR934X_DDR_REG_FLUSH_PCIE      0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC      0xac
 
 
 #define PCI_WIN0_OFFS  0x10000000
@@ -619,6 +659,7 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR933X_RESET_REG_RESET_MODULE          0x1c
 #define AR933X_RESET_REG_BOOTSTRAP             0xac
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN          BIT(18)
 #define AR933X_BOOTSTRAP_EEPBUSY               BIT(4)
 #define AR933X_BOOTSTRAP_REF_CLK_40            BIT(0)
 
@@ -868,6 +909,25 @@ void ar71xx_flash_release(void);
 #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
 #define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
 
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG                0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0     BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0       BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0      BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER        BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN        BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE    BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP     BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS   BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0      BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* __ASM_MACH_AR71XX_H */