case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
mdio_dev = &ath79_mdio1_device;
mdio_data = &ath79_mdio1_data;
break;
break;
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
mdio_data->builtin_switch = 1;
break;
case ATH79_SOC_QCA9533:
case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pll_10 = AR934X_PLL_VAL_10;
pll_100 = AR934X_PLL_VAL_100;
pll_1000 = AR934X_PLL_VAL_1000;
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
break;
}
break;
+ case ATH79_SOC_QCA9561:
+ if (!pdata->phy_if_mode)
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
+ break;
+
default:
BUG();
}
case ATH79_SOC_AR7241:
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
break;
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9533:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
iounmap(base);
}
+void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
+ unsigned int rxdv)
+{
+ void __iomem *base;
+ u32 t;
+
+ rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
+ rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
+
+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+ AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+ t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+ rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9533:
if (id == 0) {
pdata->reset_bit = AR934X_RESET_GE0_MAC |
AR934X_RESET_GE0_MDIO;
pdata->fifo_cfg3 = 0x01f00140;
break;
- case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
if (id == 0) {
pdata->reset_bit = AR933X_RESET_GE0_MAC |
AR933X_RESET_GE0_MDIO;
pdata->set_speed = ath79_set_speed_dummy;
- pdata->phy_mask = BIT(4);
+ if (!pdata->phy_mask)
+ pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit = AR933X_RESET_GE1_MAC |
AR933X_RESET_GE1_MDIO;
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9561:
+ case ATH79_SOC_TP9343:
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
break;