rev = id & AR933X_REV_ID_REVISION_MASK;
break;
+ case REV_ID_MAJOR_AR9341:
+ ar71xx_soc = AR71XX_SOC_AR9341;
+ chip = "9341";
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
case REV_ID_MAJOR_AR9342:
ar71xx_soc = AR71XX_SOC_AR9342;
chip = "9342";
{
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
+ u32 bootstrap;
- if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
+ bootstrap = ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
ar71xx_ref_freq = 40 * 1000 * 1000;
else
ar71xx_ref_freq = 25 * 1000 * 1000;