{
void __iomem *base = ar71xx_gpio_base;
unsigned long flags;
+ unsigned int reg;
+
+ if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+ ar71xx_soc == AR71XX_SOC_AR9342 ||
+ ar71xx_soc == AR71XX_SOC_AR9344) {
+ reg = AR934X_GPIO_REG_FUNC;
+ } else {
+ reg = AR71XX_GPIO_REG_FUNC;
+ }
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
- base + AR71XX_GPIO_REG_FUNC);
+ __raw_writel(__raw_readl(base + reg) | mask, base + reg);
/* flush write */
- (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
+ (void) __raw_readl(base + reg);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
{
void __iomem *base = ar71xx_gpio_base;
unsigned long flags;
+ unsigned int reg;
+
+ if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+ ar71xx_soc == AR71XX_SOC_AR9342 ||
+ ar71xx_soc == AR71XX_SOC_AR9344) {
+ reg = AR934X_GPIO_REG_FUNC;
+ } else {
+ reg = AR71XX_GPIO_REG_FUNC;
+ }
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
- base + AR71XX_GPIO_REG_FUNC);
+ __raw_writel(__raw_readl(base + reg) & ~mask, base + reg);
/* flush write */
- (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
+ (void) __raw_readl(base + reg);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
{
void __iomem *base = ar71xx_gpio_base;
unsigned long flags;
+ unsigned int reg;
+
+ if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+ ar71xx_soc == AR71XX_SOC_AR9342 ||
+ ar71xx_soc == AR71XX_SOC_AR9344) {
+ reg = AR934X_GPIO_REG_FUNC;
+ } else {
+ reg = AR71XX_GPIO_REG_FUNC;
+ }
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
- base + AR71XX_GPIO_REG_FUNC);
+ __raw_writel((__raw_readl(base + reg) & ~clear) | set, base + reg);
/* flush write */
- (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
+ (void) __raw_readl(base + reg);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
EXPORT_SYMBOL(ar71xx_gpio_function_setup);
+void __init ar71xx_gpio_output_select(unsigned gpio, u8 val)
+{
+ void __iomem *base = ar71xx_gpio_base;
+ unsigned long flags;
+ unsigned int reg;
+ u32 t, s;
+
+ if (ar71xx_soc != AR71XX_SOC_AR9341 &&
+ ar71xx_soc != AR71XX_SOC_AR9342 &&
+ ar71xx_soc != AR71XX_SOC_AR9344)
+ return;
+
+ if (gpio >= AR934X_GPIO_COUNT)
+ return;
+
+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ s = 8 * (gpio % 4);
+
+ spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+ t = __raw_readl(base + reg);
+ t &= ~(0xff << s);
+ t |= val << s;
+ __raw_writel(t, base + reg);
+
+ /* flush write */
+ (void) __raw_readl(base + reg);
+
+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
void __init ar71xx_gpio_init(void)
{
int err;
break;
case AR71XX_SOC_AR7240:
+ ar71xx_gpio_chip.ngpio = AR7240_GPIO_COUNT;
+ break;
+
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
- ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
+ ar71xx_gpio_chip.ngpio = AR7241_GPIO_COUNT;
break;
case AR71XX_SOC_AR9130:
if (err)
panic("cannot add AR71xx GPIO chip, error=%d", err);
}
+
+int gpio_to_irq(unsigned gpio)
+{
+ return AR71XX_GPIO_IRQ(gpio);
+}
+EXPORT_SYMBOL(gpio_to_irq);
+
+int irq_to_gpio(unsigned irq)
+{
+ return irq - AR71XX_GPIO_IRQ_BASE;
+}
+EXPORT_SYMBOL(irq_to_gpio);