},
};
+struct ag71xx_switch_platform_data ar71xx_switch_data;
+
#define AR71XX_PLL_VAL_1000 0x00110000
#define AR71XX_PLL_VAL_100 0x00001099
#define AR71XX_PLL_VAL_10 0x00991099
pdata->reset_bit |= RESET_MODULE_GE0_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge0;
pdata->set_speed = ar724x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit |= RESET_MODULE_GE1_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge1;
pdata->set_speed = ar724x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->switch_data = &ar71xx_switch_data;
}
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
AR933X_RESET_GE0_MDIO;
pdata->ddr_flush = ar933x_ddr_flush_ge0;
pdata->set_speed = ar933x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit = AR933X_RESET_GE1_MAC |
AR933X_RESET_GE1_MDIO;
pdata->ddr_flush = ar933x_ddr_flush_ge1;
pdata->set_speed = ar933x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->switch_data = &ar71xx_switch_data;
}
pdata->has_gbit = 1;
pdata->reset_bit = AR934X_RESET_GE1_MAC |
AR934X_RESET_GE1_MDIO;
pdata->ddr_flush = ar934x_ddr_flush_ge1;
- pdata->set_speed = ar934x_set_speed_ge1
+ pdata->set_speed = ar934x_set_speed_ge1;
+
+ pdata->switch_data = &ar71xx_switch_data;
}
pdata->has_gbit = 1;
__setup("kmac=", ar71xx_kmac_setup);
void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
- unsigned offset)
+ int offset)
{
- u32 t;
+ int t;
if (!is_valid_ether_addr(src)) {
memset(dst, '\0', ETH_ALEN);