#ifndef __ADM8668_H__
#define __ADM8668_H__
-#define SYS_CLOCK 175000000
-
/*======================= Physical Memory Map ============================*/
#define ADM8668_SDRAM_BASE 0
#define ADM8668_SMEM1_BASE 0x10000000
#define ADM8668_SMEM0_BASE 0x1FC00000
#define ADM8668_NAND_BASE 0x1FFFFF00
-#define PCICFG_BASE 0x12200000
-#define PCIDAT_BASE 0x12400000
-
-/** onboard uart **/
-#define ADM8668_UARTCLK_FREQ 62500000
-/* registers */
-#define UART_DR_REG 0x00
-#define UART_RSR_REG 0x04
-#define UART_CR_REG 0x14
-#define UART_FR_REG 0x18
-#define UART_IIR_REG 0x1C
-
-/* rsr reg */
-#define UART_FRAMING_ERR 0x01
-#define UART_PARITY_ERR 0x02
-#define UART_BREAK_ERR 0x04
-#define UART_OVERRUN_ERR 0x08
-#define UART_RX_STATUS_MASK 0x0F
-
-/* cr reg */
-#define UART_RX_INT_EN 0x10
-#define UART_TX_INT_EN 0x20
-#define UART_RX_TIMEOUT_INT_EN 0x40
-
-/* fr reg */
-#define UART_RX_FIFO_EMPTY 0x10
-#define UART_TX_FIFO_FULL 0x20
-
-/* iir reg */
-#define UART_RX_INT 0x02
-#define UART_TX_INT 0x04
-#define UART_RX_TIMEOUT_INT 0x08
-
-/* interrupt controller */
-#define IRQ_STATUS_REG 0x00 /* Read */
-#define IRQ_ENABLE_REG 0x08 /* Read/Write */
-#define IRQ_DISABLE_REG 0x0C /* Write */
+#define ADM8668_PCICFG_BASE 0x12200000
+#define ADM8668_PCIDAT_BASE 0x12400000
/* interrupt levels */
#define INT_LVL_SWI 1
#define INT_LVL_MAX INT_LVL_USB
/* register access macros */
-#define ADM8668_INTC_REG(_reg) \
- (*((volatile unsigned long *)(KSEG1ADDR(ADM8668_INTC_BASE + (_reg)))))
#define ADM8668_LAN_REG(_reg) \
(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
#define ADM8668_WAN_REG(_reg) \
#define CRGPIO_TOGGLE(num) \
ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
+void adm8668_init_clocks(void);
+
#endif /* __ADM8668_H__ */