#define WAIT_FOR_RF(__dev, __reg) \
rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
#define WAIT_FOR_MCU(__dev, __reg) \
-@@ -186,19 +188,55 @@
+@@ -186,19 +188,55 @@ static void rt2800_rfcsr_write(struct rt
* Wait until the RFCSR becomes available, afterwards we
* can safely write the new data into the register.
*/
static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
const unsigned int word, u8 *value)
{
-@@ -214,22 +252,47 @@
+@@ -214,22 +252,47 @@ static void rt2800_rfcsr_read(struct rt2
* doesn't become available in time, reg will be 0xffffffff
* which means we return 0xff to the caller.
*/
static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
const unsigned int word, const u32 value)
{
-@@ -566,6 +629,16 @@
+@@ -566,6 +629,16 @@ void rt2800_get_txwi_rxwi_size(struct rt
*rxwi_size = RXWI_DESC_SIZE_5WORDS;
break;
case RT5592:
*txwi_size = TXWI_DESC_SIZE_5WORDS;
*rxwi_size = RXWI_DESC_SIZE_6WORDS;
-@@ -3326,6 +3399,312 @@
+@@ -3302,6 +3375,312 @@ static void rt2800_config_channel_rf55xx
rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
}
+ u32 mac_sys_ctrl, mac_status;
+ u32 tx_pin = 0x00150F0F;
+ struct hw_mode_spec *spec = &rt2x00dev->spec;
++ struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
+
+ /* Frequeny plan setting */
+ /*
+ rfcsr &= (~0x4);
+ rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
+
-+ struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
+ /*if (bScan == FALSE)*/
+ if (conf_is_ht40(conf)) {
+ txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
const unsigned int word,
const u8 value)
-@@ -3482,7 +3861,7 @@
+@@ -3458,7 +3837,7 @@ static void rt2800_config_channel(struct
struct channel_info *info)
{
u32 reg;
u8 bbp, rfcsr;
info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
-@@ -3536,6 +3915,9 @@
+@@ -3512,6 +3891,9 @@ static void rt2800_config_channel(struct
case RF5592:
rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
break;
default:
rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
}
-@@ -3638,7 +4020,7 @@
+@@ -3614,7 +3996,7 @@ static void rt2800_config_channel(struct
else if (rt2x00_rt(rt2x00dev, RT3593) ||
rt2x00_rt(rt2x00dev, RT3883))
rt2800_bbp_write(rt2x00dev, 82, 0x82);
rt2800_bbp_write(rt2x00dev, 82, 0xf2);
if (rt2x00_rt(rt2x00dev, RT3593) ||
-@@ -3660,7 +4042,7 @@
+@@ -3636,7 +4018,7 @@ static void rt2800_config_channel(struct
if (rt2x00_rt(rt2x00dev, RT3572))
rt2800_rfcsr_write(rt2x00dev, 8, 0);
switch (rt2x00dev->default_ant.tx_chain_num) {
case 3:
-@@ -3709,6 +4091,7 @@
+@@ -3685,6 +4067,7 @@ static void rt2800_config_channel(struct
rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
-@@ -4718,6 +5101,14 @@
+@@ -4701,6 +5084,14 @@ void rt2800_vco_calibration(struct rt2x0
rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
break;
default:
return;
}
-@@ -5118,9 +5509,42 @@
+@@ -5101,9 +5492,42 @@ static int rt2800_init_registers(struct
} else if (rt2x00_rt(rt2x00dev, RT5390) ||
rt2x00_rt(rt2x00dev, RT5392) ||
rt2x00_rt(rt2x00dev, RT5592)) {
} else if (rt2x00_rt(rt2x00dev, RT5350)) {
rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
} else {
-@@ -6152,6 +6576,225 @@
+@@ -6135,6 +6559,225 @@ static void rt2800_init_bbp_5592(struct
rt2800_bbp_write(rt2x00dev, 103, 0xc0);
}
static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
{
unsigned int i;
-@@ -6194,7 +6837,10 @@
+@@ -6177,7 +6820,10 @@ static void rt2800_init_bbp(struct rt2x0
return;
case RT5390:
case RT5392:
break;
case RT5592:
rt2800_init_bbp_5592(rt2x00dev);
-@@ -7408,6 +8054,295 @@
+@@ -7391,6 +8037,296 @@ static void rt2800_init_rfcsr_5592(struc
rt2800_led_open_drain_enable(rt2x00dev);
}
+{
+ u16 freq;
+ u8 rfvalue;
++ struct hw_mode_spec *spec = &rt2x00dev->spec;
++
+ /* Initialize RF central register to default value */
+ rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
+ rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
+ rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
+
-+ struct hw_mode_spec *spec = &rt2x00dev->spec;
+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
+ if (spec->clk_is_20mhz)
+ rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
{
if (rt2800_is_305x_soc(rt2x00dev)) {
-@@ -7443,7 +8378,10 @@
+@@ -7426,7 +8362,10 @@ static void rt2800_init_rfcsr(struct rt2
rt2800_init_rfcsr_5350(rt2x00dev);
break;
case RT5390:
break;
case RT5392:
rt2800_init_rfcsr_5392(rt2x00dev);
-@@ -7875,6 +8813,7 @@
+@@ -7858,6 +8797,7 @@ static int rt2800_init_eeprom(struct rt2
case RF5390:
case RF5392:
case RF5592:
break;
default:
rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
-@@ -8441,6 +9380,7 @@
+@@ -8422,6 +9362,7 @@ static int rt2800_probe_hw_mode(struct r
case RF5372:
case RF5390:
case RF5392:
spec->num_channels = 14;
if (spec->clk_is_20mhz)
spec->channels = rf_vals_xtal20mhz_3x;
-@@ -8581,6 +9521,7 @@
+@@ -8562,6 +9503,7 @@ static int rt2800_probe_hw_mode(struct r
case RF5372:
case RF5390:
case RF5392: