/******************/
/* Chip Revisions */
/******************/
-@@ -1337,6 +1350,9 @@ static bool ath9k_hw_set_reset(struct at
+@@ -1348,6 +1361,9 @@ static bool ath9k_hw_set_reset(struct at
if (AR_SREV_9100(ah))
udelay(50);
return true;
}
-@@ -1436,6 +1452,9 @@ static bool ath9k_hw_chip_reset(struct a
+@@ -1447,6 +1463,9 @@ static bool ath9k_hw_chip_reset(struct a
ar9003_hw_internal_regulator_apply(ah);
ath9k_hw_init_pll(ah, chan);
return true;
}
-@@ -1730,8 +1749,14 @@ static int ath9k_hw_do_fastcc(struct ath
+@@ -1741,8 +1760,14 @@ static int ath9k_hw_do_fastcc(struct ath
if (AR_SREV_9271(ah))
ar9002_hw_load_ani_reg(ah, chan);
return -EINVAL;
}
-@@ -1959,6 +1984,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
- if (AR_SREV_9565(ah) && common->bt_ant_diversity)
- REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
+@@ -1990,6 +2015,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+ ath9k_hw_set_radar_params(ah);
+ }
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+ ath9k_hw_disable_pll_lock_detect(ah);