Merge branch 'master' of git://git.denx.de/u-boot-usb

[oweals/u-boot.git] / lib_blackfin / cache.c

diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index 847278d226ed3114bfd709d28878b2786c27c26e..1557864f9c4470492f779bac012c9c5560cd0401 100644 (file)
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -1,40 +1,71 @@
 /*
  * U-boot - cache.c
  *
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2008 Analog Devices Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Licensed under the GPL-2 or later.
  */
 
-/* for now: just dummy functions to satisfy the linker */
-extern void blackfin_icache_range (unsigned long *, unsigned long *);
-extern void blackfin_dcache_range (unsigned long *, unsigned long *);
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+       void *start_addr, *end_addr;
+       int istatus, dstatus;
+
+       /* no need to flush stuff in on chip memory (L1/L2/etc...) */
+       if (addr >= 0xE0000000)
+               return;
+
+       start_addr = (void *)addr;
+       end_addr = (void *)(addr + size);
+       istatus = icache_status();
+       dstatus = dcache_status();
+
+       if (istatus) {
+               if (dstatus)
+                       blackfin_icache_dcache_flush_range(start_addr, end_addr);
+               else
+                       blackfin_icache_flush_range(start_addr, end_addr);
+       } else if (dstatus)
+               blackfin_dcache_flush_range(start_addr, end_addr);
+}
+
+void icache_enable(void)
+{
+       bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+       SSYNC();
+}
+
+void icache_disable(void)
+{
+       bfin_write_IMEM_CONTROL(0);
+       SSYNC();
+}
+
+int icache_status(void)
+{
+       return bfin_read_IMEM_CONTROL() & IMC;
+}
+
+void dcache_enable(void)
+{
+       bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+       SSYNC();
+}
+
+void dcache_disable(void)
+{
+       bfin_write_DMEM_CONTROL(0);
+       SSYNC();
+}
+
+int dcache_status(void)
 {
-       if (icache_status ()) {
-               blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
-       }
-       if (dcache_status ()) {
-               blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
-       }
-       return;
+       return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
 }