configs: Resync with savedefconfig

[oweals/u-boot.git] / include / ppc_asm.tmpl

diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 53141b1f716b8f9a63b3077161cf4404683239bb..db7b1668d99a60ecd3992f0e090b37a7f0c23e00 100644 (file)
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -81,22 +80,49 @@
 #define        r30     30
 #define        r31     31
 
+#if defined(CONFIG_MPC8xx)
+
+/* Some special registers */
+
+#define ICR    148     /* Interrupt Cause Register (37-44) */
+#define DER    149
+#define COUNTA 150     /* Breakpoint Counter       (37-44) */
+#define COUNTB 151     /* Breakpoint Counter       (37-44) */
+#define LCTRL1 156     /* Load/Store Support       (37-40) */
+#define LCTRL2 157     /* Load/Store Support       (37-41) */
+#define ICTRL  158
+
+#endif /* CONFIG_MPC8xx */
+
+
+#if defined(CONFIG_MPC8xx)
+
+/* Registers in the processor's internal memory map that we use.
+*/
+#define SYPCR  0x00000004
+#define BR0    0x00000100
+#define OR0    0x00000104
+#define BR1    0x00000108
+#define OR1    0x0000010c
+#define BR2    0x00000110
+#define OR2    0x00000114
+#define BR3    0x00000118
+#define OR3    0x0000011c
+#define BR4    0x00000120
+#define OR4    0x00000124
 
-#if  defined(CONFIG_5xx)
-/* Some special purpose registers */
-#define DER    149             /* Debug Enable Register                */
-#define COUNTA 150             /* Breakpoint Counter                   */
-#define COUNTB 151             /* Breakpoint Counter                   */
-#define LCTRL1 156             /* Load/Store Support                   */
-#define LCTRL2 157             /* Load/Store Support                   */
-#define ICTRL  158             /* I-Bus Support Control Register       */
-#define EID    81
-#endif /* CONFIG_5xx */
+#define MAR    0x00000164
+#define MCR    0x00000168
+#define MAMR   0x00000170
+#define MBMR   0x00000174
+#define MSTAT  0x00000178
+#define MPTPR  0x0000017a
+#define MDR    0x0000017c
 
-#if defined(CONFIG_MPC5xxx)
+#define TBSCR  0x00000200
+#define TBREFF0        0x00000204
 
-#define HID0_ICE_BITPOS        16
-#define HID0_DCE_BITPOS        17
+#define PLPRCR 0x00000284
 
 #endif