Coldfire M5271: Activate u-boot system timer interrupt.

[oweals/u-boot.git] / include / ppc4xx.h

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index e216663a86de7a4a1864a0af10ad6bfc07f61e82..55ff32353a1091d7d70fe8b94b9c856dfe3d44ea 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,13 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||        \
+    defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||  \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_NAND_NDFC
+#endif
+
 /* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
@@ -107,8 +114,8 @@
  * Enable long long (%ll ...) printf format on 440 PPC's since most of
  * them support 36bit physical addressing
  */
-#define CFG_64BIT_VSPRINTF
-#define CFG_64BIT_STRTOUL
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
 #include <ppc440.h>
 #else
 #include <ppc405.h>
@@ -143,7 +150,7 @@
 #define _START_OFFSET          (EXC_OFF_SYS_RESET + 0x2000)
 
 #define RESET_VECTOR   0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
                                                     line aligned data. */
 
 #define CPR0_DCR_BASE  0x0C
@@ -218,4 +225,7 @@ static inline void set_mcsr(u32 val)
 
 #endif /* __ASSEMBLY__ */
 
+/* for multi-cpu support */
+#define NA_OR_UNKNOWN_CPU      -1
+
 #endif /* __PPC4XX_H__ */