ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,

[oweals/u-boot.git] / include / ppc4xx.h

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index c71da6084405cedde696408679eedab84e134faf..e1613ddcc848eb5ed9ee7179073e24a100bd4988 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,62 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_460SX)
+
+#define PLB_ARBITER_BASE               0x80
+
+#define plb0_revid                     (PLB_ARBITER_BASE+ 0x00)
+#define plb0_acr                       (PLB_ARBITER_BASE+ 0x01)
+#define plb0_acr_ppm_mask              0xF0000000
+#define plb0_acr_ppm_fixed             0x00000000
+#define plb0_acr_ppm_fair              0xD0000000
+#define plb0_acr_hbu_mask              0x08000000
+#define plb0_acr_hbu_disabled          0x00000000
+#define plb0_acr_hbu_enabled           0x08000000
+#define plb0_acr_rdp_mask              0x06000000
+#define plb0_acr_rdp_disabled          0x00000000
+#define plb0_acr_rdp_2deep             0x02000000
+#define plb0_acr_rdp_3deep             0x04000000
+#define plb0_acr_rdp_4deep             0x06000000
+#define plb0_acr_wrp_mask              0x01000000
+#define plb0_acr_wrp_disabled          0x00000000
+#define plb0_acr_wrp_2deep             0x01000000
+
+#define plb0_besrl                     (PLB_ARBITER_BASE+ 0x02)
+#define plb0_besrh                     (PLB_ARBITER_BASE+ 0x03)
+#define plb0_bearl                     (PLB_ARBITER_BASE+ 0x04)
+#define plb0_bearh                     (PLB_ARBITER_BASE+ 0x05)
+#define plb0_ccr                       (PLB_ARBITER_BASE+ 0x08)
+
+#define plb1_acr                       (PLB_ARBITER_BASE+ 0x09)
+#define plb1_acr_ppm_mask              0xF0000000
+#define plb1_acr_ppm_fixed             0x00000000
+#define plb1_acr_ppm_fair              0xD0000000
+#define plb1_acr_hbu_mask              0x08000000
+#define plb1_acr_hbu_disabled          0x00000000
+#define plb1_acr_hbu_enabled           0x08000000
+#define plb1_acr_rdp_mask              0x06000000
+#define plb1_acr_rdp_disabled          0x00000000
+#define plb1_acr_rdp_2deep             0x02000000
+#define plb1_acr_rdp_3deep             0x04000000
+#define plb1_acr_rdp_4deep             0x06000000
+#define plb1_acr_wrp_mask              0x01000000
+#define plb1_acr_wrp_disabled          0x00000000
+#define plb1_acr_wrp_2deep             0x01000000
+
+#define plb1_besrl                     (PLB_ARBITER_BASE+ 0x0A)
+#define plb1_besrh                     (PLB_ARBITER_BASE+ 0x0B)
+#define plb1_bearl                     (PLB_ARBITER_BASE+ 0x0C)
+#define plb1_bearh                     (PLB_ARBITER_BASE+ 0x0D)
+
+#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
+
 #if defined(CONFIG_440)
 /*
  * Enable long long (%ll ...) printf format on 440 PPC's since most of