ppx4xx: Fix sdram init on PMC440 boards

[oweals/u-boot.git] / include / ppc405.h

diff --git a/include/ppc405.h b/include/ppc405.h
index 4d2514425e22be8efe80fb8dfacb7ace6250a2c5..b5ad38fc527a9ec79c33069c90ee6741d3db06a7 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -22,6 +22,12 @@
 #ifndef        __PPC405_H__
 #define __PPC405_H__
 
+#ifndef CONFIG_IOP480
+#define CFG_DCACHE_SIZE                (16 << 10)      /* For AMCC 405 CPUs    */
+#else
+#define CFG_DCACHE_SIZE                (2 << 10)       /* For PLX IOP480 (403) */
+#endif
+
 /*--------------------------------------------------------------------- */
 /* Special Purpose Registers                                           */
 /*--------------------------------------------------------------------- */
@@ -344,9 +350,6 @@
 /******************************************************************************
  * SDRAM Controller
  ******************************************************************************/
-#define SDRAM_DCR_BASE 0x10
-#define memcfga  (SDRAM_DCR_BASE+0x0)   /* Memory configuration address reg  */
-#define memcfgd  (SDRAM_DCR_BASE+0x1)   /* Memory configuration data    reg  */
   /* values for memcfga register - indirect addressing of these regs */
 #ifndef CONFIG_405EP
   #define mem_besra   0x00    /* bus error syndrome reg a           */
@@ -412,9 +415,6 @@
 /******************************************************************************
  * Extrnal Bus Controller
  ******************************************************************************/
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0)   /* External bus controller addr reg     */
-#define ebccfgd (EBC_DCR_BASE+0x1)   /* External bus controller data reg     */
   /* values for ebccfga register - indirect addressing of these regs */
   #define pb0cr       0x00    /* periph bank 0 config reg            */
   #define pb1cr       0x01    /* periph bank 1 config reg            */
@@ -1135,6 +1135,8 @@
 
 #endif /* CONFIG_405EZ */
 
+#define GPIO0_BASE             GPIO_BASE
+
 #if defined(CONFIG_405EX)
 #define SDR0_SRST              0x0200
 
@@ -1572,58 +1574,19 @@
 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
-#endif
 
-/******************************************************************************
- * SDR Registers
- ******************************************************************************/
-#define SDR_DCR_BASE   0x0E
-#define sdrcfga                (SDR_DCR_BASE+0x0)
-#define sdrcfgd                (SDR_DCR_BASE+0x1)
-
-#define CPR0_DCR_BASE  0x0C
-#define cprcfga                (CPR0_DCR_BASE+0x0)
-#define cprcfgd                (CPR0_DCR_BASE+0x1)
-
-#define mtcpr(reg, d)  do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
-#define mfcpr(reg, d)  do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
-
-#define mtsdr(reg, d)  do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
-#define mfsdr(reg, d)  do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
-
-#define mtebc(reg, d)  do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
-#define mfebc(reg, d)  do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
-
-#define mtsdram(reg, d)        do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
-#define mfsdram(reg, d)        do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
-       unsigned long pllFwdDiv;
-       unsigned long pllFwdDivB;
-       unsigned long pllFbkDiv;
-       unsigned long pllPlbDiv;
-       unsigned long pllPciDiv;
-       unsigned long pllExtBusDiv;
-       unsigned long pllOpbDiv;
-       unsigned long freqVCOMhz;       /* in MHz                          */
-       unsigned long freqProcessor;
-       unsigned long freqPLB;
-       unsigned long freqPCI;
-       unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
-       unsigned long pciClkSync;       /* PCI clock is synchronous        */
-       unsigned long freqVCOHz;
-       unsigned long freqOPB;
-       unsigned long freqEBC;
-       unsigned long freqDDR;
-} PPC405_SYS_INFO;
-
-#endif  /* _ASMLANGUAGE */
-
-#define RESET_VECTOR   0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
-                                                    line aligned data. */
+#define SDR0_PFC0              0x4100
+#define SDR0_PFC1              0x4101
+#define SDR0_PFC1_U1ME         0x02000000
+#define SDR0_PFC1_U0ME         0x00080000
+#define SDR0_PFC1_U0IM         0x00040000
+#define SDR0_PFC1_SIS          0x00020000
+#define SDR0_PFC1_DMAAEN       0x00010000
+#define SDR0_PFC1_DMADEN       0x00008000
+#define SDR0_PFC1_USBEN                0x00004000
+#define SDR0_PFC1_AHBSWAP      0x00000020
+#define SDR0_PFC1_USBBIGEN     0x00000010
+#define SDR0_PFC1_GPT_FREQ     0x0000000f
+#endif
 
 #endif /* __PPC405_H__ */