ZOOM2 Add led support.

[oweals/u-boot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 191488aa89938d2454438bdd36878b717435c9e3..fab37516cf8b11f5ea22c08b8c45d8f7f4c4f2ae 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -266,6 +266,7 @@
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A                    0xC0000000
 #define SICRL_USB_B                    0x30000000
+#define SICRL_USB_B_SD                 0x20000000
 #define SICRL_UART                     0x0C000000
 #define SICRL_GPIO_A                   0x02000000
 #define SICRL_GPIO_B                   0x01000000
@@ -307,10 +308,12 @@
 #define SICRH_GPIO2_C                  0x00002000
 #define SICRH_GPIO2_D                  0x00001000
 #define SICRH_GPIO2_E                  0x00000C00
+#define SICRH_GPIO2_E_SD               0x00000800
 #define SICRH_GPIO2_F                  0x00000300
 #define SICRH_GPIO2_G                  0x000000C0
 #define SICRH_GPIO2_H                  0x00000030
 #define SICRH_SPI                      0x00000003
+#define SICRH_SPI_SD                   0x00000001
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -887,6 +890,8 @@
 #define TIMING_CFG1_CASLAT_30          0x00050000      /* CAS latency = 3.0 */
 #define TIMING_CFG1_CASLAT_35          0x00060000      /* CAS latency = 3.5 */
 #define TIMING_CFG1_CASLAT_40          0x00070000      /* CAS latency = 4.0 */
+#define TIMING_CFG1_CASLAT_45          0x00080000      /* CAS latency = 4.5 */
+#define TIMING_CFG1_CASLAT_50          0x00090000      /* CAS latency = 5.0 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */