Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 39cecf21c2b52729d2b5a665fbf5e8a6ebfa9b37..d2e1e2bb6c8705256568decada830cd0b3f5d25c 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -48,71 +48,36 @@
 
 /* SPRIDR - System Part and Revision ID Register
  */
-#define SPRIDR_PARTID                  0xFFFF0000      /* Part Identification */
-#define SPRIDR_REVID                   0x0000FFFF      /* Revision Identification */
-
-#define SPR_8349E_REV10                        0x80300100
-#define SPR_8349_REV10                 0x80310100
-#define SPR_8347E_REV10_TBGA           0x80320100
-#define SPR_8347_REV10_TBGA            0x80330100
-#define SPR_8347E_REV10_PBGA           0x80340100
-#define SPR_8347_REV10_PBGA            0x80350100
-#define SPR_8343E_REV10                        0x80360100
-#define SPR_8343_REV10                 0x80370100
-
-#define SPR_8349E_REV11                        0x80300101
-#define SPR_8349_REV11                 0x80310101
-#define SPR_8347E_REV11_TBGA           0x80320101
-#define SPR_8347_REV11_TBGA            0x80330101
-#define SPR_8347E_REV11_PBGA           0x80340101
-#define SPR_8347_REV11_PBGA            0x80350101
-#define SPR_8343E_REV11                        0x80360101
-#define SPR_8343_REV11                 0x80370101
-
-#define SPR_8349E_REV31                        0x80300300
-#define SPR_8349_REV31                 0x80310300
-#define SPR_8347E_REV31_TBGA           0x80320300
-#define SPR_8347_REV31_TBGA            0x80330300
-#define SPR_8347E_REV31_PBGA           0x80340300
-#define SPR_8347_REV31_PBGA            0x80350300
-#define SPR_8343E_REV31                        0x80360300
-#define SPR_8343_REV31                 0x80370300
-
-#define SPR_8360E_REV10                        0x80480010
-#define SPR_8360_REV10                 0x80490010
-#define SPR_8360E_REV11                        0x80480011
-#define SPR_8360_REV11                 0x80490011
-#define SPR_8360E_REV12                        0x80480012
-#define SPR_8360_REV12                 0x80490012
-#define SPR_8360E_REV20                        0x80480020
-#define SPR_8360_REV20                 0x80490020
-#define SPR_8360E_REV21                        0x80480021
-#define SPR_8360_REV21                 0x80490021
-
-#define SPR_8323E_REV10                        0x80620010
-#define SPR_8323_REV10                 0x80630010
-#define SPR_8321E_REV10                        0x80660010
-#define SPR_8321_REV10                 0x80670010
-#define SPR_8323E_REV11                        0x80620011
-#define SPR_8323_REV11                 0x80630011
-#define SPR_8321E_REV11                        0x80660011
-#define SPR_8321_REV11                 0x80670011
-
-#define SPR_8313E_REV10                        0x80B00010
-#define SPR_8313_REV10                 0x80B10010
-#define SPR_8311E_REV10                        0x80B20010
-#define SPR_8311_REV10                 0x80B30010
-#define SPR_8315E_REV10                        0x80B40010
-#define SPR_8315_REV10                 0x80B50010
-#define SPR_8314E_REV10                        0x80B60010
-#define SPR_8314_REV10                 0x80B70010
-
-#define SPR_8379E_REV10                        0x80C20010
-#define SPR_8379_REV10                 0x80C30010
-#define SPR_8378E_REV10                        0x80C40010
-#define SPR_8378_REV10                 0x80C50010
-#define SPR_8377E_REV10                        0x80C60010
-#define SPR_8377_REV10                 0x80C70010
+#define SPRIDR_PARTID                  0xFFFF0000      /* Part Id */
+#define SPRIDR_REVID                   0x0000FFFF      /* Revision Id */
+
+#if defined(CONFIG_MPC834X)
+#define REVID_MAJOR(spridr)            ((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr)            (spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr)            ((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr)            (spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr)            ((spridr & 0xFFFE0000) >> 16)
+#define IS_E_PROCESSOR(spridr)         (!(spridr & 0x00010000)) /* has SEC */
+
+#define SPR_8311                       0x80B2
+#define SPR_8313                       0x80B0
+#define SPR_8314                       0x80B6
+#define SPR_8315                       0x80B4
+#define SPR_8321                       0x8066
+#define SPR_8323                       0x8062
+#define SPR_8343                       0x8036
+#define SPR_8347_TBGA_                 0x8032
+#define SPR_8347_PBGA_                 0x8034
+#define SPR_8349                       0x8030
+#define SPR_8358_TBGA_                 0x804A
+#define SPR_8358_PBGA_                 0x804E
+#define SPR_8360                       0x8048
+#define SPR_8377                       0x80C6
+#define SPR_8378                       0x80C4
+#define SPR_8379                       0x80C2
 
 /* SPCR - System Priority Configuration Register
  */
@@ -121,6 +86,7 @@
 #define SPCR_PCIPR                     0x03000000      /* PCI bridge system bus request priority */
 #define SPCR_PCIPR_SHIFT               (31-7)
 #define SPCR_OPT                       0x00800000      /* Optimize */
+#define SPCR_OPT_SHIFT                 (31-8)
 #define SPCR_TBEN                      0x00400000      /* E300 PowerPC core time base unit enable */
 #define SPCR_TBEN_SHIFT                        (31-9)
 #define SPCR_COREPR                    0x00300000      /* E300 PowerPC Core system bus request priority */
@@ -725,6 +691,7 @@
 #define SCCR_USBCM_3                   0x00F00000
 
 #elif defined(CONFIG_MPC8313)
+/* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
 #define SCCR_TSEC1CM_0                 0x00000000
@@ -732,13 +699,6 @@
 #define SCCR_TSEC1CM_2                 0x80000000
 #define SCCR_TSEC1CM_3                 0xC0000000
 
-#define SCCR_TSEC2CM                   0x30000000
-#define SCCR_TSEC2CM_SHIFT             28
-#define SCCR_TSEC2CM_0                 0x00000000
-#define SCCR_TSEC2CM_1                 0x10000000
-#define SCCR_TSEC2CM_2                 0x20000000
-#define SCCR_TSEC2CM_3                 0x30000000
-
 #define SCCR_TSEC1ON                   0x20000000
 #define SCCR_TSEC1ON_SHIFT             29
 #define SCCR_TSEC2ON                   0x10000000
@@ -838,6 +798,8 @@
 #define SCCR_PCIEXP2CM_3               0x000c0000
 
 /* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM                   0x000000c0
+#define SCCR_SATA1CM_SHIFT             6
 #define SCCR_SATACM                    0x000000ff
 #define SCCR_SATACM_SHIFT              0
 #define SCCR_SATACM_0                  0x00000000
@@ -884,7 +846,7 @@
 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT  16
 #define TIMING_CFG0_ODT_PD_EXIT                0x00000F00
 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT  8
-#define TIMING_CFG0_MRS_CYC            0x00000F00
+#define TIMING_CFG0_MRS_CYC            0x0000000F
 #define TIMING_CFG0_MRS_CYC_SHIFT      0
 
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
@@ -907,6 +869,7 @@
 #define TIMING_CFG1_WRTORD_SHIFT       0
 #define TIMING_CFG1_CASLAT_20          0x00030000      /* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25          0x00040000      /* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30          0x00050000      /* CAS latency = 2.5 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */