mx6sabreauto: Convert to DM_ETH

[oweals/u-boot.git] / include / i2c.h

diff --git a/include/i2c.h b/include/i2c.h
index 33570f5404f144f07ef9ec2682ff9ad2a521d688..0faf8542e283ac97007adeb6566d12dd5f8c8399 100644 (file)
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -30,6 +30,32 @@ enum dm_i2c_chip_flags {
        DM_I2C_CHIP_WR_ADDRESS  = 1 << 2, /* Send address for each write byte */
 };
 
+/** enum i2c_speed_mode - standard I2C speed modes */
+enum i2c_speed_mode {
+       IC_SPEED_MODE_STANDARD,
+       IC_SPEED_MODE_FAST,
+       IC_SPEED_MODE_FAST_PLUS,
+       IC_SPEED_MODE_HIGH,
+       IC_SPEED_MODE_FAST_ULTRA,
+
+       IC_SPEED_MODE_COUNT,
+};
+
+/** enum i2c_speed_rate - standard I2C speeds in Hz */
+enum i2c_speed_rate {
+       I2C_SPEED_STANDARD_RATE         = 100000,
+       I2C_SPEED_FAST_RATE             = 400000,
+       I2C_SPEED_FAST_PLUS_RATE        = 1000000,
+       I2C_SPEED_HIGH_RATE             = 3400000,
+       I2C_SPEED_FAST_ULTRA_RATE       = 5000000,
+};
+
+/** enum i2c_address_mode - available address modes */
+enum i2c_address_mode {
+       I2C_MODE_7_BIT,
+       I2C_MODE_10_BIT
+};
+
 struct udevice;
 /**
  * struct dm_i2c_chip - information about an i2c chip
@@ -45,12 +71,26 @@ struct udevice;
  *             represent up to 256 bytes. A value larger than 1 may be
  *             needed for larger devices.
  * @flags:     Flags for this chip (dm_i2c_chip_flags)
+ * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for
+ *                        devices which steal addresses as part of offset.
+ *                        If offset_len is zero, then the offset is encoded
+ *                        completely within the chip address itself.
+ *                        e.g. a devce with chip address of 0x2c with 512
+ *                        registers might use the bottom bit of the address
+ *                        to indicate which half of the address space is being
+ *                        accessed while still only using 1 byte offset.
+ *                        This means it will respond to  chip address 0x2c and
+ *                        0x2d.
+ *                        A real world example is the Atmel AT24C04. It's
+ *                        datasheet explains it's usage of this addressing
+ *                        mode.
  * @emul: Emulator for this chip address (only used for emulation)
  */
 struct dm_i2c_chip {
        uint chip_addr;
        uint offset_len;
        uint flags;
+       uint chip_addr_offset_mask;
 #ifdef CONFIG_SANDBOX
        struct udevice *emul;
        bool test_mode;
@@ -261,6 +301,25 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
  */
 int i2c_get_chip_offset_len(struct udevice *dev);
 
+/**
+ * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset
+ *
+ * Some devices listen on multiple chip addresses to achieve larger offsets
+ * than their single or multiple byte offsets would allow for. You can use this
+ * function to set the bits that are valid to be used for offset overflow.
+ *
+ * @mask: The mask to be used for high offset bits within address
+ * @return 0 if OK, other -ve value on error
+ */
+int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask);
+
+/*
+ * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset
+ *
+ * @return current chip addr offset mask
+ */
+uint i2c_get_chip_addr_offset_mask(struct udevice *dev);
+
 /**
  * i2c_deblock() - recover a bus that is in an unknown state
  *