ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay...

[oweals/u-boot.git] / include / fsl_sec.h

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index ebb1ac6d40f233d01a2b59d01017dd62e389b48b..672bcef2f3b71f97c045e3552be122ad8b33f279 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -32,10 +32,20 @@
 /* RNG4 TRNG test registers */
 struct rng4tst {
 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
+                                                   both entropy shifter and
+                                                   statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
+                                                   entropy shifter and
+                                                   statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+                                                   entropy shifter, raw data
+                                                   in statistical checker */
+#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
        u32 rtmctl;             /* misc. control register */
        u32 rtscmisc;           /* statistical check misc. register */
        u32 rtpkrrng;           /* poker range register */
-#define RTSDCTL_ENT_DLY_MIN    1200
+#define RTSDCTL_ENT_DLY_MIN    3200
 #define RTSDCTL_ENT_DLY_MAX    12800
        union {
                u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
@@ -49,6 +59,7 @@ struct rng4tst {
                u32 rttotsam;   /* PRGM=0: total samples register */
        };
        u32 rtfreqmin;          /* frequency count min. limit register */
+#define RTFRQMAX_DISABLE       (1 << 20)
        union {
                u32 rtfreqmax;  /* PRGM=1: freq. count max. limit register */
                u32 rtfreqcnt;  /* PRGM=0: freq. count register */