ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay...

[oweals/u-boot.git] / include / fsl_sec.h

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c84b6ad8d8fb310f0fc4137eb40c7e9fd1b695d6..672bcef2f3b71f97c045e3552be122ad8b33f279 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -32,6 +32,16 @@
 /* RNG4 TRNG test registers */
 struct rng4tst {
 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
+                                                   both entropy shifter and
+                                                   statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
+                                                   entropy shifter and
+                                                   statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+                                                   entropy shifter, raw data
+                                                   in statistical checker */
+#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
        u32 rtmctl;             /* misc. control register */
        u32 rtscmisc;           /* statistical check misc. register */
        u32 rtpkrrng;           /* poker range register */