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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
[oweals/u-boot.git]
/
include
/
fsl_immap.h
diff --git
a/include/fsl_immap.h
b/include/fsl_immap.h
index d63cc19fa159d0efcdc9cbf81c5f9b9a4537c77c..e4addada13045a714abe1de18643c1b02b183560 100644
(file)
--- a/
include/fsl_immap.h
+++ b/
include/fsl_immap.h
@@
-87,9
+87,7
@@
struct ccsr_ddr {
u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
u8 res_258[0x260-0x258];
u32 sdram_cfg_3;
- u8 res_264[0x2a0-0x264];
- u32 deskew_cntl;
- u8 res_2a4[0x400-0x2a4];
+ u8 res_264[0x400-0x264];
u32 dq_map_0;
u32 dq_map_1;
u32 dq_map_2;