dm: core: Add uclass_first_device_err() to return a valid device

[oweals/u-boot.git] / include / fsl_ddr_sdram.h

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index c79fce089826f65cc6a5aa7ceddc3d6ab63e30d4..3699c0408a11aeeee2354b471e5a63174f12d924 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,9 +1,7 @@
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef FSL_DDR_MEMCTL_H
@@ -33,6 +31,15 @@
 #define DDR3_RTT_20_OHM                4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM                5 /* RTT_Nom = RZQ/8 */
 
+#define DDR4_RTT_OFF           0
+#define DDR4_RTT_60_OHM                1       /* RZQ/4 */
+#define DDR4_RTT_120_OHM       2       /* RZQ/2 */
+#define DDR4_RTT_40_OHM                3       /* RZQ/6 */
+#define DDR4_RTT_240_OHM       4       /* RZQ/1 */
+#define DDR4_RTT_48_OHM                5       /* RZQ/5 */
+#define DDR4_RTT_80_OHM                6       /* RZQ/3 */
+#define DDR4_RTT_34_OHM                7       /* RZQ/7 */
+
 #define DDR2_RTT_OFF           0
 #define DDR2_RTT_75_OHM                1
 #define DDR2_RTT_150_OHM       2
@@ -122,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG2_ODT_ONLY_READ       2
 #define SDRAM_CFG2_ODT_ALWAYS          3
 
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
 #define TIMING_CFG_2_CPO_MASK  0x0F800000
 
 #if defined(CONFIG_SYS_FSL_DDR_VER) && \