phy: atheros: Clarify the intention of ar8021_config

[oweals/u-boot.git] / include / fsl_ddr.h

diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index feccef9c9cd16b2311d60ed82c4a742bf7389b0f..2476f40c56d6cc37dab08fefa7c59ea1bbb5e3a1 100644 (file)
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
  */
 
 #ifndef FSL_DDR_MAIN_H
@@ -17,7 +14,7 @@
 
 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
 /* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      CONFIG_SYS_NUM_DDR_CTLRS
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR_LE
@@ -34,9 +31,7 @@
 #define ddr_clrsetbits32(a, clear, set)        clrsetbits_be32(a, clear, set)
 #endif
 
-#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
-
-u32 fsl_ddr_get_version(void);
+u32 fsl_ddr_get_version(unsigned int ctrl_num);
 
 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
@@ -58,7 +53,6 @@ compute_dimm_parameters(const unsigned int ctrl_num,
  *
  * All data structures have to be on the stack
  */
-#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
 
 typedef struct {
@@ -105,7 +99,7 @@ unsigned int compute_lowest_common_dimm_parameters(
                                const dimm_params_t *dimm_params,
                                common_timing_params_t *outpdimm,
                                unsigned int number_of_dimms);
-unsigned int populate_memctl_options(int all_dimms_registered,
+unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
                                memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num);
@@ -133,9 +127,15 @@ void board_add_ram_info(int use_default);
 /* processor specific function */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                                   unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
 
 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
                        unsigned int controller_number,
                        unsigned int dimm_number);
+void update_spd_address(unsigned int ctrl_num,
+                       unsigned int slot,
+                       unsigned int *addr);
+
+void erratum_a009942_check_cpo(void);
 #endif