#define MC_CCSR_BASE_ADDR \
((struct mc_ccsr_registers __iomem *)0x8340000)
-#define BIT(x) (1 << (x))
#define GCR1_P1_STOP BIT(31)
#define GCR1_P2_STOP BIT(30)
#define GCR1_P1_DE_RST BIT(23)
#define GCR1_M2_DE_RST BIT(14)
#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
#define GSR_FS_MASK 0x3fffffff
-#define MCFAPR_PL_MASK (0x1 << 18)
-#define MCFAPR_BMT_MASK (0x1 << 17)
-#define MCFAPR_BYPASS_ICID_MASK \
- (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
+#define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
#define SOC_MC_PORTAL_STRIDE 0x10000
#define SOC_MC_PORTAL_ADDR(_portal_id) \
u32 reg_error[];
};
-int mc_init(bd_t *bis);
-
int get_mc_boot_status(void);
+unsigned long mc_get_dram_block_size(void);
+int fsl_mc_ldpaa_init(bd_t *bis);
+void fsl_mc_ldpaa_exit(bd_t *bis);
#endif