ARM: tegra: enable CONFIG_SYS_NONCACHED_MEMORY everywhere

[oweals/u-boot.git] / include / fsl-mc / fsl_mc.h

diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index 28d596184eb4f7373c17e89a5d24e4e2edaa5b1d..9517a4a7b5d753ba2beb49b8f14a00f04794244f 100644 (file)
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -12,7 +12,6 @@
 #define MC_CCSR_BASE_ADDR \
        ((struct mc_ccsr_registers __iomem *)0x8340000)
 
-#define BIT(x)                 (1 << (x))
 #define GCR1_P1_STOP           BIT(31)
 #define GCR1_P2_STOP           BIT(30)
 #define GCR1_P1_DE_RST         BIT(23)
@@ -21,12 +20,9 @@
 #define GCR1_M2_DE_RST         BIT(14)
 #define GCR1_M_ALL_DE_RST      (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
 #define GSR_FS_MASK            0x3fffffff
-#define MCFAPR_PL_MASK         (0x1 << 18)
-#define MCFAPR_BMT_MASK                (0x1 << 17)
-#define MCFAPR_BYPASS_ICID_MASK        \
-       (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
 
 #define SOC_MC_PORTALS_BASE_ADDR    ((void __iomem *)0x00080C000000)
+#define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
 #define SOC_MC_PORTAL_STRIDE       0x10000
 
 #define SOC_MC_PORTAL_ADDR(_portal_id) \
@@ -53,8 +49,8 @@ struct mc_ccsr_registers {
        u32 reg_error[];
 };
 
-int mc_init(bd_t *bis);
-
 int get_mc_boot_status(void);
 unsigned long mc_get_dram_block_size(void);
+int fsl_mc_ldpaa_init(bd_t *bis);
+void fsl_mc_ldpaa_exit(bd_t *bis);
 #endif