#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS 1
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR 0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/*
* Diagnostics
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
+ CONFIG_SYS_I2C_DS4510_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_PEX8518_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_END 0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
* Use the HUSH parser
*/
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Pass open firmware flat tree
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_NET_MULTI 1
#define CONFIG_TSEC_TBI
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \