tegra: i2c: Select number of controllers for Tegra2 boards

[oweals/u-boot.git] / include / configs / xilinx-ppc.h

diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index b4a96759355a2834562bcc6ae9cda39aebbe376c..bd7bac097634adb45eb605f9091ea22c20225961 100644 (file)
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -50,6 +50,7 @@
 #undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS
 
 /*Misc*/
 #define CONFIG_BOOTDELAY               5/* autoboot after 5 seconds     */
@@ -91,10 +92,9 @@
 
 /*Stack*/
 #define CONFIG_SYS_INIT_RAM_ADDR       0x800000/* Initial RAM address    */
-#define CONFIG_SYS_INIT_RAM_END                0x2000  /* End of used area in RAM  */
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* num bytes initial data   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END \
-                               - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE               0x2000  /* Size of used area in RAM  */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE \
+                               - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 /*Speed*/
 #define CONFIG_SYS_CLK_FREQ    XPAR_CORE_CLOCK_FREQ_HZ