powerpc/85xx: Fix NAND SPL support

[oweals/u-boot.git] / include / configs / tuxa1.h

diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
index 012db96736e6e9ce169ef9abe27f59dccbb94dcd..2d9af3f525f5ad907e27ab594d7325108a08e6ff 100644 (file)
--- a/include/configs/tuxa1.h
+++ b/include/configs/tuxa1.h
@@ -33,7 +33,7 @@
 #define        CONFIG_SYS_TEXT_BASE    0xF0000000
 
 /* include common defines/options for all 8321 Keymile boards */
-#include "km8321-common.h"
+#include "km/km8321-common.h"
 
 #define        CONFIG_SYS_LPXF_BASE            0xA0000000    /* LPXF */
 #define        CONFIG_SYS_LPXF_SIZE            256 /* Megabytes */
@@ -67,8 +67,8 @@
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
-                                (OR_GPCM_TRLX & \
-                                (~OR_GPCM_EHTR)) |  /* EHTR = 0 */ \
+                                OR_GPCM_TRLX_SET | \
+                                OR_GPCM_EHTR_CLEAR | \
                                 OR_GPCM_EAD)
 /*
  * PINC2 on the local bus CS3
@@ -85,11 +85,10 @@
 
 #define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
                                 OR_GPCM_CSNT | \
-                                (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
-                                (~OR_GPCM_XACS)) |  /* XACS = 0 */ \
-                                (OR_GPCM_SCY_2 & \
-                                (~OR_GPCM_EHTR)) |  /* EHTR = 0 */ \
-                                OR_GPCM_TRLX)
+                                OR_GPCM_ACS_DIV2 | \
+                                OR_GPCM_SCY_2 | \
+                                OR_GPCM_TRLX_SET | \
+                                OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_MAMR                (MxMR_GPL_x4DIS | \
                                 0x0000c000 | \
@@ -99,20 +98,20 @@
  * MMU Setup
  */
 /* LPXF:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT5U      (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
                                 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
 
 /* PINC2:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
                                 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U