arc: add Arcangel4 board support

[oweals/u-boot.git] / include / configs / ti_am335x_common.h

diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 03726f257c715d9057cbeb29091c9c2f255b8c71..4364eef7ba82e00a7b068a036262398a8efefcf1 100644 (file)
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
 #define CONFIG_SYS_TIMERBASE           0x48040000      /* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #include <asm/arch/omap.h>
 
@@ -42,11 +43,15 @@
 
 /*
  * RTC related defines. To use bootcount you must set bootlimit in the
- * environment to a non-zero value.
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
+ * in the board config.
  */
-#define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_SYS_BOOTCOUNT_ADDR      0x44E3E000
 
+/* Enable the HW watchdog, since we can use this with bootcount */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x402F0400 and 0x4030B800 as a download area and
@@ -57,6 +62,9 @@
 #define CONFIG_SPL_TEXT_BASE           0x402F0400
 #define CONFIG_SPL_MAX_SIZE            (0x4030B800 - CONFIG_SPL_TEXT_BASE)
 
+/* Enable the watchdog inside of SPL */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 /*
  * Since SPL did pll and ddr initialization for us,
  * we don't need to do it twice.