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ARM: tegra: Make cache line size SoC specific
[oweals/u-boot.git]
/
include
/
configs
/
tegra114-common.h
diff --git
a/include/configs/tegra114-common.h
b/include/configs/tegra114-common.h
index 44e98e501952bb26284b531323aee68c9621e9c3..c3de9a999e952e3f893a6ae9efa2538e53b79e3e 100644
(file)
--- a/
include/configs/tegra114-common.h
+++ b/
include/configs/tegra114-common.h
@@
-18,6
+18,9
@@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* NS16550 Configuration
*/