Merge with /home/mk/11-cmb1920/u-boot#4upstream

[oweals/u-boot.git] / include / configs / spc1920.h

diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index c6b4d3002b782d3c00bfd1bfddda160f57723a80..09bbebdce899407d9e390c77092e05682cde7b15 100644 (file)
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -51,12 +51,12 @@
 #define CFG_8xx_CPUCLK_MIN             40000000
 #define CFG_8xx_CPUCLK_MAX             133000000
 
-#define CFG_RESET_ADDRESS              0xf8000000
+#define CFG_RESET_ADDRESS              0xC0000000
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_LAST_STAGE_INIT
 
-
-#if 1
+#if 0
 #define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
 #else
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
@@ -89,7 +89,6 @@
                         | CFG_CMD_JFFS2 \
                         | CFG_CMD_PING \
                         | CFG_CMD_DHCP \
-                        | CFG_CMD_IMMAP \
                         | CFG_CMD_I2C \
                         | CFG_CMD_MII)
                        /* & ~( CFG_CMD_NET)) */
@@ -248,7 +247,7 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR     (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR      (SIUMCR_FRC)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control                                11-26
@@ -311,7 +310,7 @@
  * FLASH timing:
  */
 #define CFG_OR_TIMING_FLASH    (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-                                OR_SCY_3_CLK | OR_EHTR | OR_BI)
+                                OR_SCY_6_CLK | OR_EHTR | OR_BI)
 
 #define CFG_OR0_REMAP  (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -362,14 +361,14 @@
  * DSP Host Port Interface CS3
  */
 #define CFG_SPC1920_HPI_BASE   0x90000000
-#define CFG_PRELIM_OR3_AM      0xF0000000
+#define CFG_PRELIM_OR3_AM      0xF8000000
 
-#define CFG_OR3_PRELIM         (CFG_PRELIM_OR3_AM | \
+#define CFG_OR3         (CFG_PRELIM_OR3_AM | \
                                       OR_G5LS | \
                                       OR_SCY_0_CLK | \
                                       OR_BI)
 
-#define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
+#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
                                               BR_MS_UPMA | \
                                               BR_PS_16 | \
                                               BR_V);
@@ -384,19 +383,32 @@
 #define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
 #define HPI_HPIC_1             HPI_REG(0)
 #define HPI_HPIC_2             HPI_REG(2)
-#define HPI_HPIA_1             HPI_REG(0x2000000)
-#define HPI_HPIA_2             HPI_REG(0x2000000 + 2)
-#define HPI_HPID_INC_1         HPI_REG(0x1000000)
-#define HPI_HPID_INC_2         HPI_REG(0x1000000 + 2)
-#define HPI_HPID_NOINC_1       HPI_REG(0x3000000)
-#define HPI_HPID_NOINC_2       HPI_REG(0x3000000 + 2)
+#define HPI_HPIA_1             HPI_REG(0x2000008)
+#define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
+#define HPI_HPID_INC_1         HPI_REG(0x1000004)
+#define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
+#define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
+#define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
 #endif /* CONFIG_SPC1920_HPI_TEST */
 
 /*
- * PLD CS5 
+ * Ramtron FM18L08 FRAM 32KB on CS4
+ */
+#define CFG_SPC1920_FRAM_BASE  0x80100000
+#define CFG_PRELIM_OR4_AM      0xffff8000
+#define CFG_OR4                (CFG_PRELIM_OR4_AM | \
+                                       OR_ACS_DIV2 | \
+                                       OR_BI | \
+                                       OR_SCY_4_CLK | \
+                                       OR_TRLX)
+
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/*
+ * PLD CS5
  */
 #define CFG_SPC1920_PLD_BASE   0x80000000
-#define CFG_PRELIM_OR5_AM      0xfff00000
+#define CFG_PRELIM_OR5_AM      0xffff8000
 
 #define CFG_OR5_PRELIM         (CFG_PRELIM_OR5_AM | \
                                        OR_CSNT_SAM | \