/* High Level Configuration Options */
#define CONFIG_SOCRATES 1
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
-/* Serial Port */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
* General PCI
* Memory space is mapped 1-1.
*/
-#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
/* PCI is clocked by the external source at 33 MHz */
#define CONFIG_PCI_CLK_FREQ 33000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
-#if defined(CONFIG_PCI)
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC3 1
/* USB support */
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_PCI_OHCI 1
-#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
-#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1