Merged POST framework with the current TOT.

[oweals/u-boot.git] / include / configs / sequoia.h

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c26eb9e6974e9c39fcab19ce0804a03a1c8..32199929a972cc6c9d2736fd2af451121dccdf73 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -37,10 +37,11 @@
 #else
 #define CONFIG_440GRX          1               /* Specific PPC440GRx   */
 #endif
+#define CONFIG_440             1               /* ... PPC440 family    */
 #define CONFIG_4xx             1               /* ... PPC4xx family    */
 /* Detect Sequoia PLL input clock automatically via CPLD bit           */
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
-                               3333333 : 33000000)
+                               33333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1            /* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R     1               /* Call misc_init_r     */
@@ -58,6 +59,7 @@
 #define CFG_MONITOR_BASE       TEXT_BASE
 #define CFG_NAND_ADDR          0xd0000000      /* NAND Flash           */
 #define CFG_OCM_BASE           0xe0010000      /* ocm                  */
+#define CFG_OCM_DATA_ADDR      CFG_OCM_BASE
 #define CFG_PCI_BASE           0xe0000000      /* Internal PCI regs    */
 #define CFG_PCI_MEMBASE                0x80000000      /* mapped pci memory    */
 #define CFG_PCI_MEMBASE1       CFG_PCI_MEMBASE  + 0x10000000
@@ -80,7 +82,7 @@
 #define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256             /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET     CFG_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -125,7 +127,7 @@
 #define CFG_FLASH_QUIET_TEST   1       /* don't warn upon unknown flash        */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE      0x20000         /* size of one complete sector  */
+#define CFG_ENV_SECT_SIZE      0x20000 /* size of one complete sector          */
 #define CFG_ENV_ADDR           ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 
@@ -168,12 +170,19 @@
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE     (512)           /* NAND chip page size          */
+#define CFG_NAND_PAGE_SIZE     512             /* NAND chip page size          */
 #define CFG_NAND_BLOCK_SIZE    (16 << 10)      /* NAND chip block size         */
-#define CFG_NAND_PAGE_COUNT    (32)            /* NAND chip page count         */
-#define CFG_NAND_BAD_BLOCK_POS (5)             /* Location of bad block marker */
+#define CFG_NAND_PAGE_COUNT    32              /* NAND chip page count         */
+#define CFG_NAND_BAD_BLOCK_POS 5               /* Location of bad block marker */
 #undef CFG_NAND_4_ADDR_CYCLE                   /* No fourth addr used (<=32MB) */
 
+#define CFG_NAND_ECCSIZE       256
+#define CFG_NAND_ECCBYTES      3
+#define CFG_NAND_ECCSTEPS      (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE       16
+#define CFG_NAND_ECCTOTAL      (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS                {0, 1, 2, 3, 6, 7}
+
 #ifdef CFG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
@@ -320,6 +329,22 @@
                               CFG_CMD_SDRAM    |       \
                               CMD_USB)
 
+/* POST support */
+#define CONFIG_POST            (CFG_POST_MEMORY   | \
+                                CFG_POST_CPU      | \
+                                CFG_POST_UART     | \
+                                CFG_POST_I2C      | \
+                                CFG_POST_CACHE    | \
+                                CFG_POST_FPU      | \
+                                CFG_POST_ETHER    | \
+                                CFG_POST_SPR)
+
+#define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR    0x10000000 /* free virtual address      */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
 #define CONFIG_SUPPORT_VFAT
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -363,7 +388,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT               /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT