/*
- * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007,2009 Wind River Systems <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
* Copyright 2004, 2007 Freescale Semiconductor.
*
/*
* sbc8548 board configuration file
- *
- * Please refer to doc/README.sbc85xx for more info.
- *
+ * Please refer to doc/README.sbc8548 for more info.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI1
+#endif
+
+#ifdef CONFIG_MK_66
+#define CONFIG_SYS_CLK_DIV 1
+#endif
+
+#ifdef CONFIG_MK_33
+#define CONFIG_SYS_CLK_DIV 2
+#endif
+
+#ifdef CONFIG_MK_PCIE
+#define CONFIG_PCIE1
+#endif
+
+/*
+ * High Level Configuration Options
+ */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#ifdef CONFIG_PCI
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+/*
+ * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
+ * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
+ * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
+ * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
+ * thing for MONITOR_LEN in both cases.
+ */
+#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
+#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
+#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
+#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#else
+#warning undefined environment size/location.
+#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI