apalis/colibri imx6: provide proper fdtfile value

[oweals/u-boot.git] / include / configs / sbc8349.h

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 775bbe417afc57dabb745c741f9bf3fff893e1d4..d2053cc0597a8bf85f2f4c99766d77d636a6c5ea 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -46,9 +46,7 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
@@ -125,16 +123,6 @@
 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)    /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*