ppc4xx: Update DU440 config

[oweals/u-boot.git] / include / configs / sbc2410x.h

diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 9b05bd6c8c24cfa92926188af76f8e7ca2438a56..110ab3904dfd9987b1a87af18e7c88b0f067ce45 100644 (file)
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -57,7 +57,7 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN         (CFG_ENV_SIZE + 128*1024)
+#define CFG_MALLOC_LEN         (CONFIG_ENV_SIZE + 128*1024)
 #define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
 
 /*
@@ -106,7 +106,9 @@
 
 
 #define CONFIG_BOOTDELAY       3
-#define CONFIG_BOOTARGS        "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_BOOTARGS                "console=ttySAC0 root=/dev/nfs " \
+               "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
+               "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
 #define CONFIG_ETHADDR         08:00:3e:26:0a:5b
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR          192.168.0.69
@@ -178,21 +180,21 @@
 #ifdef CONFIG_AMD_LV800
 #define PHYS_FLASH_SIZE                0x00100000 /* 1MB */
 #define CFG_MAX_FLASH_SECT     (19)    /* max number of sectors on one chip */
-#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#define CONFIG_ENV_ADDR                (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
 #endif
 
 #ifdef CONFIG_AMD_LV400
 #define PHYS_FLASH_SIZE                0x00080000 /* 512KB */
 #define CFG_MAX_FLASH_SECT     (11)    /* max number of sectors on one chip */
-#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#define CONFIG_ENV_ADDR                (CFG_FLASH_BASE + 0x070000) /* addr of environment */
 #endif
 
 /* timeout values are in ticks */
 #define CFG_FLASH_ERASE_TOUT   (5*CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT   (5*CFG_HZ) /* Timeout for Flash Write */
 
-#define        CFG_ENV_IS_IN_FLASH     1
-#define CFG_ENV_SIZE           0x10000 /* Total Size of Environment Sector */
+#define        CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SIZE                0x10000 /* Total Size of Environment Sector */
 
 /*-----------------------------------------------------------------------
  * NAND flash settings
@@ -205,7 +207,7 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_ChipID_UNKNOWN    0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1