Merge with git://www.denx.de/git/u-boot.git

[oweals/u-boot.git] / include / configs / p3p440.h

diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 831d018e2d47c3abc61c0806b2abc7d0bb19ba01..22f9f84ec23c151837df249e0297b9c5903ec26e 100644 (file)
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -35,6 +35,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_P3P440          1           /* Board is P3P440          */
 #define CONFIG_440GP           1           /* Specifc GP support       */
+#define CONFIG_440             1           /* ... PPC440 family        */
 #define CONFIG_4xx             1           /* ... PPC4xx family        */
 #define CONFIG_BOARD_EARLY_INIT_F 1        /* Call board_early_init_f  */
 #define CONFIG_MISC_INIT_R     1           /* Call misc_init_r         */
@@ -71,9 +72,10 @@
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SDRAM_BANK0     1       /* init onboard DDR SDRAM bank 0*/
-#define CFG_SDRAM_TABLE        {       \
-               {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
-               {(64 << 20),  0x00082001}} /* 64MB mode 2, 12x9(4)   */
+#define CONFIG_SDRAM_ECC               /* enable ECC support           */
+#define CFG_SDRAM_TABLE        { \
+               {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+               {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -146,6 +148,7 @@
                "cp.b 100000 fffc0000 40000;"                           \
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
+       "unlock=yes\0"                                                  \
        ""
 #define CONFIG_BOOTCOMMAND     "run net_nfs"
 
@@ -224,7 +227,6 @@
 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT                /* let board init pci target    */
 
 #define CONFIG_DISABLE_PISE_TEST       /* disable PISE test (PCIX only)*/
@@ -275,12 +277,15 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
+#define CFG_FLASH_USE_BUFFER_WRITE 1   /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION   1       /* use hardware flash protection        */
+
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST   1       /* don't warn upon unknown flash        */
 
 #define CFG_ENV_IS_IN_FLASH     1      /* use FLASH for environment vars       */
 
-#define CFG_ENV_SECT_SIZE      0x20000         /* size of one complete sector  */
+#define CFG_ENV_SECT_SIZE      0x20000 /* size of one complete sector          */
 #define CFG_ENV_ADDR           (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */