tegra: fdt: Enable FDT support for Seaboard

[oweals/u-boot.git] / include / configs / omap3_sdp3430.h

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 35472bb044916721f7bf53b7b3e334ca10624e36..404aed2f5f9cbe7a1becc1ff7b97ae3be34ab2c6 100644 (file)
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -38,7 +38,6 @@
  */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
-#define CONFIG_OMAP3430                1       /* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP   1       /* working with SDP Rev2 */
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
@@ -138,9 +137,6 @@
 #define CONFIG_SYS_I2C_BUS_SELECT      1
 #define CONFIG_DRIVER_OMAP34XX_I2C     1
 
-/* DDR - I use Infineon DDR */
-#define CONFIG_OMAP3_INFINEON_DDR      1
-
 /* OMITTED:  single 1 Gbit MT29F1G NAND flash */
 
 /*
@@ -304,10 +300,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE       (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ   (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ   (4 << 10) /* FIQ stack */
-#endif
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
@@ -323,9 +315,6 @@
 #define PHYS_SDRAM_1_SIZE      (32 << 20) /* at least 32 meg */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C             1
-
 /*--------------------------------------------------------------------------*/
 
 /*
@@ -358,4 +347,6 @@
  *  - rest for filesystem
  */
 
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
 #endif                         /* __CONFIG_H */