8xxx: Second UART port added for MPC85xx, MPC83xx, MPC86xx processors
[oweals/u-boot.git] / include / configs / omap3_evm.h
index 1b309504051a4be5ebcd5536cf482710c38dd9fa..e205c01b4b72dd947eea45b3a0aaccaf7307dc8a 100644 (file)
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of */
                                                        /* NAND devices */
-#define SECTORSIZE                     512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN                    1
-#define ADDR_PAGE                      2
-#define ADDR_COLUMN_PAGE               3
-
-#define NAND_ChipID_UNKNOWN            0x00
-#define NAND_MAX_FLOORS                        1
-#define NAND_MAX_CHIPS                 1
-#define NAND_NO_RB                     1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 /* Environment information */
 #define CONFIG_BOOTDELAY       10
 
+#define CONFIG_BOOTFILE                uImage
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "loadaddr=0x82000000\0" \
        "console=ttyS2,115200n8\0" \
                                                                /* address */
 
 /*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE           OMAP34XX_GPT2
-#define CONFIG_SYS_PTV                 7       /* 2^(PTV+1) */
-#define CONFIG_SYS_HZ                  ((V_SCLK) / (2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV                 2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ                  1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -304,23 +295,6 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-                       writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-                       writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------