apalis/colibri imx6: provide proper fdtfile value
[oweals/u-boot.git] / include / configs / mx6ul_14x14_evk.h
index 733538f2eea2564129234d6c2ad358c1f8a8cf19..42e511591c60d8a80621e964e4b52533997bdd54 100644 (file)
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  *
  * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef __MX6UL_14X14_EVK_CONFIG_H
 #define __MX6UL_14X14_EVK_CONFIG_H
 
 /* I2C configs */
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED           100000
+#endif
 
-/* PMIC only for 9X9 EVK */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR  0x08
+#ifdef CONFIG_DM_GPIO
+#define CONFIG_DM_74X164
 #endif
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
 #define CONFIG_SYS_HZ                  1000
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 #define CONFIG_SYS_MMC_ENV_PART                0       /* user area */
 #define CONFIG_MMCROOT                 "/dev/mmcblk1p2"  /* USDHC2 */
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_SF_DEFAULT_BUS          0
-#define CONFIG_SF_DEFAULT_CS           0
-#define CONFIG_SF_DEFAULT_SPEED        40000000
-#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SYS_FSL_QSPI_AHB
 #define FSL_QSPI_FLASH_NUM             1
 #define FSL_QSPI_FLASH_SIZE            SZ_32M
 #endif
 
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_MXC
-#define CONFIG_MII
 #define CONFIG_FEC_ENET_DEV            1
 
 #if (CONFIG_FEC_ENET_DEV == 0)
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR          0x2
 #define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                        "eth0"
 #elif (CONFIG_FEC_ENET_DEV == 1)
 #define IMX_FEC_BASE                   ENET2_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR         0x1
 #define CONFIG_FEC_XCV_TYPE            RMII
+#define CONFIG_ETHPRIME                        "eth1"
 #endif
-#define CONFIG_ETHPRIME                        "FEC"
 #endif
 
 #define CONFIG_IMX_THERMAL