Merge tag 'efi-2020-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / include / configs / mpc8308_p1m.h

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 046355f64547d7bb2c0807ef039aec3dee8a7407..3ce4b705b7073c034034fd9e0270de4d2cb0d95b 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -21,31 +21,6 @@
 #define CONFIG_TSEC1
 #define CONFIG_TSEC2
 
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
-       SICRH_ESDHC_A_GPIO |\
-       SICRH_ESDHC_B_GPIO |\
-       SICRH_ESDHC_C_GTM |\
-       SICRH_GPIO_A_TSEC2 |\
-       SICRH_GPIO_B_TSEC2_TX_CLK |\
-       SICRH_IEEE1588_A_GPIO |\
-       SICRH_USB |\
-       SICRH_GTM_GPIO |\
-       SICRH_IEEE1588_B_GPIO |\
-       SICRH_ETSEC2_CRS |\
-       SICRH_GPIOSEL_1 |\
-       SICRH_TMROBI_V3P3 |\
-       SICRH_TSOBI1_V3P3 |\
-       SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
-#define CONFIG_SYS_SICRL (\
-       SICRL_SPI_PF0 |\
-       SICRL_UART_PF0 |\
-       SICRL_IRQ_PF0 |\
-       SICRL_I2C2_PF0 |\
-       SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
-
 #define CONFIG_SYS_GPIO1_PRELIM
 /* GPIO Default input/output settings */
 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
@@ -55,30 +30,16 @@
  */
 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
 
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
 /*
  * SERDES
  */
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1     0xe3000
 
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP        3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT  3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \
@@ -164,13 +125,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP           LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-
 /*
  * FLASH on the Local Bus
  */
@@ -179,19 +133,6 @@
 #define CONFIG_SYS_FLASH_BASE          0xFC000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          64 /* FLASH size is 64M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_64MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_4 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512
@@ -205,27 +146,13 @@
  * SJA1000 CAN controller on Local Bus
  */
 #define CONFIG_SYS_SJA1000_BASE        0xFBFF0000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_SJA1000_BASE \
-                               | BR_PS_8       /* 8 bit port size */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_SCY_5 \
-                               | OR_GPCM_EHTR_SET)
-                               /* 0xFFFF8052 */
+
 
 /*
  * CPLD on Local Bus
  */
 #define CONFIG_SYS_CPLD_BASE   0xFBFF8000
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_CPLD_BASE \
-                               | BR_PS_8       /* 8 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_SCY_4 \
-                               | OR_GPCM_EHTR_SET)
-                               /* 0xFFFF8042 */
+
 
 /*
  * Serial Port
@@ -336,15 +263,6 @@
  */
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20) /* Initial Memory map for Linux */
 
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE | \
-                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2                HID2_HBE
-
 /*
  * Environment Configuration
  */