Merge branch 'sandbox' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / include / configs / mpc8308_p1m.h

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 6784c2ea5a46551499abefa1377a5da94e88b262..20fc6418b97032334ea84aef26abc8fee6de442a 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -157,9 +157,11 @@
 
 #define CONFIG_SYS_DDR_CS0_BNDS        0x00000007
 #define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
-                               | 0x00010000  /* ODT_WR to CSn */ \
-                               | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-                               /* 0x80010102 */
+                                       | CSCONFIG_ODT_RD_NEVER \
+                                       | CSCONFIG_ODT_WR_ONLY_CURRENT \
+                                       | CSCONFIG_ROW_BIT_13 \
+                                       | CSCONFIG_COL_BIT_10)
+                                       /* 0x80010102 */
 #define CONFIG_SYS_DDR_TIMING_3        0x00000000
 #define CONFIG_SYS_DDR_TIMING_0        ((0 << TIMING_CFG0_RWT_SHIFT) \
                                | (0 << TIMING_CFG0_WRT_SHIFT) \
@@ -192,7 +194,7 @@
                                /* 0x03600100 */
 #define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SREN \
                                | SDRAM_CFG_SDRAM_TYPE_DDR2 \
-                               | SDRAM_CFG_32_BE)
+                               | SDRAM_CFG_DBW_32)
                                /* 0x43080000 */
 
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000 /* 1 posted refresh */
@@ -246,18 +248,18 @@
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_64MB)
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE  /* Flash Base addr */ \
-                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR0_PRELIM  ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
+                               | BR_PS_16      /* 16 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_4 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512
@@ -272,11 +274,12 @@
  */
 #define CONFIG_SYS_SJA1000_BASE        0xFBFF0000
 #define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_SJA1000_BASE \
-                               | (1 << BR_PS_SHIFT)    /* 8 bit port */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000             /* length 32K */ \
+                               | BR_PS_8       /* 8 bit port size */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
                                | OR_GPCM_SCY_5 \
-                               | OR_GPCM_EHTR)
+                               | OR_GPCM_EHTR_SET)
                                /* 0xFFFF8052 */
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_SJA1000_BASE
@@ -287,11 +290,12 @@
  */
 #define CONFIG_SYS_CPLD_BASE   0xFBFF8000
 #define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_CPLD_BASE \
-                               | (1 << BR_PS_SHIFT)    /* 8 bit port */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR2_PRELIM  (0xFFFF8000             /* length 32K */ \
+                               | BR_PS_8       /* 8 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB \
                                | OR_GPCM_SCY_4 \
-                               | OR_GPCM_EHTR)
+                               | OR_GPCM_EHTR_SET)
                                /* 0xFFFF8042 */
 
 #define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_CPLD_BASE
@@ -454,7 +458,7 @@
  */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
                                        BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
                                        BATU_VS | BATU_VP)
@@ -462,7 +466,7 @@
 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_RW | \
                        BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
                                        BATU_VP)
@@ -470,17 +474,17 @@
 #define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                        BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT2U      (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
                                        BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                        BATL_CACHEINHIBIT | \
                                        BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
                                        BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L