Merge with /home/m8/git/u-boot

[oweals/u-boot.git] / include / configs / ml300.h

diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index d93925ee66ce130a19ce1447d4904cb4db6f55ae..6762cd61eae5b50d11a259e592bfa588a90a8d3d 100644 (file)
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -38,7 +38,7 @@
  *     You should have received a copy of the GNU General Public License along
  *     with this program; if not, write to the Free Software Foundation, Inc.,
  *     675 Mass Ave, Cambridge, MA 02139, USA.
-  *
+ *
  */
 
 #ifndef __CONFIG_H
@@ -56,9 +56,26 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_XILINX_ML300    1       /* ...on a Xilinx ML300 board   */
 
-#define CFG_ENV_IS_NOWHERE     1       /* environment is in RAM */
+#define CONFIG_SYSTEMACE       1
+#define CONFIG_DOS_PARTITION   1
+#define CFG_SYSTEMACE_BASE     XPAR_OPB_SYSACE_0_BASEADDR
+#define CFG_SYSTEMACE_WIDTH    XPAR_XSYSACE_MEM_WIDTH
+
+#define CFG_ENV_IS_IN_EEPROM   1       /* environment is in EEPROM */
+
+/* following are used only if env is in EEPROM */
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_I2C_EEPROM_ADDR    XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_ENV_OFFSET         XPAR_PERSISTENT_0_IIC_0_BASEADDR
+#define CONFIG_MISC_INIT_R     1       /* used to call out convert_env() */
+#define CONFIG_ENV_OVERWRITE   1       /* allow users to update ethaddr and serial# */
+#endif
+
+#include "../board/xilinx/ml300/xparameters.h"
+
 #define CFG_NO_FLASH           1       /* no flash */
-#define CFG_ENV_SIZE           0x2000
+#define CFG_ENV_SIZE           XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
 #define CONFIG_BAUDRATE                9600
 #define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
 
@@ -130,7 +147,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs     */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs    */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 
 /*-----------------------------------------------------------------------