arm: socfpga: cyclone5_socdk: Enable qspiload console command

[oweals/u-boot.git] / include / configs / microblaze-generic.h

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index e16965c56c8960c41438e7fd1b2f25e35c857f9e..f93861d770ee3effe181ae050cea09ec0775c686 100644 (file)
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -39,7 +39,6 @@
 # define CONFIG_SYS_BAUDRATE_TABLE     { CONFIG_BAUDRATE }
 # define CONSOLE_ARG   "console=console=ttyUL0,115200\0"
 #elif XILINX_UART16550_BASEADDR
-# define CONFIG_SYS_NS16550            1
 # define CONFIG_SYS_NS16550_SERIAL
 # if defined(__MICROBLAZEEL__)
 #  define CONFIG_SYS_NS16550_REG_SIZE  -4
@@ -69,10 +68,6 @@
 # define CONFIG_XILINX_EMACLITE        1
 # define CONFIG_SYS_ENET
 #endif
-#if defined(XILINX_LLTEMAC_BASEADDR)
-# define CONFIG_XILINX_LL_TEMAC        1
-# define CONFIG_SYS_ENET
-#endif
 #if defined(XILINX_AXIEMAC_BASEADDR)
 # define CONFIG_XILINX_AXIEMAC 1
 # define CONFIG_SYS_ENET
@@ -102,26 +97,24 @@
 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
 # define CONFIG_WATCHDOG_BASEADDR      XILINX_WATCHDOG_BASEADDR
 # define CONFIG_WATCHDOG_IRQ           XILINX_WATCHDOG_IRQ
-# define CONFIG_HW_WATCHDOG
-# define CONFIG_XILINX_TB_WATCHDOG
+# ifndef CONFIG_SPL_BUILD
+#  define CONFIG_HW_WATCHDOG
+#  define CONFIG_XILINX_TB_WATCHDOG
+# endif
 #endif
 
-#ifndef CONFIG_OF_CONTROL
+#if !defined(CONFIG_OF_CONTROL) || \
+       (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
 /* ddr sdram - main memory */
 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
 #endif
 
 #define CONFIG_SYS_MALLOC_LEN  0xC0000
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_SYS_MALLOC_F_LEN       1024
-#else
-# define CONFIG_SYS_MALLOC_SIMPLE
-# define CONFIG_SYS_MALLOC_F_LEN       0x150
-#endif
 
 /* Stack location before relocation */
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_TEXT_BASE - \
+                                        CONFIG_SYS_MALLOC_F_LEN)
 
 /*
  * CFI flash memory layout - Example
@@ -174,9 +167,7 @@
 #ifdef SPIFLASH
 # define CONFIG_SYS_NO_FLASH           1
 # define CONFIG_SYS_SPI_BASE           XILINX_SPI_FLASH_BASEADDR
-# define CONFIG_XILINX_SPI             1
 # define CONFIG_SPI                    1
-# define CONFIG_SPI_FLASH_STMICRO      1
 # define CONFIG_SF_DEFAULT_MODE                SPI_MODE_3
 # define CONFIG_SF_DEFAULT_SPEED       XILINX_SPI_FLASH_MAX_FREQ
 # define CONFIG_SF_DEFAULT_CS          XILINX_SPI_FLASH_CS
@@ -247,7 +238,6 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MFSL
-#define CONFIG_CMD_GPIO
 
 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
 # define CONFIG_CMD_CACHE
@@ -316,8 +306,6 @@
                                "1m(cramfs),-(jffs2)"
 #endif
 
-/* Miscellaneous configurable options */
-#define        CONFIG_SYS_PROMPT       "U-Boot-mONStR> "
 /* size of console buffer */
 #define        CONFIG_SYS_CBSIZE       512
  /* print buffer size */
@@ -365,7 +353,7 @@
 #define CONFIG_FIT             1
 #define CONFIG_OF_LIBFDT       1
 
-#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
+#if defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII            1
 # define CONFIG_CMD_MII                1
 # define CONFIG_PHY_GIGE       1