#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | \
- CSCONFIG_ODT_WR_ACS)
+ CSCONFIG_ODT_WR_ONLY_CURRENT)
-#define CONFIG_SYS_DDRCDR 0x40000001
+#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
+ /* 0x40000001 */
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000
* PAXE on the local bus CS3
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+ BR_PS_8 | /* 8 bit port size */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
+ OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* MMU Setup