Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

[oweals/u-boot.git] / include / configs / km / km83xx-common.h

diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 85b6ed200474dbd72ce46c6163a8c562912df2dd..06ecb8a3e96ca78f2dbe4785705c7f02b83accb9 100644 (file)
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -103,16 +103,17 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+                               BR_PS_16 | /* 16 bit port size */ \
+                               BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX | OR_GPCM_EAD)
+                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -123,15 +124,16 @@
  */
 /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000001A /* 128MB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_128MB)
 
 #define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+                               BR_PS_8 | /* 8 bit port size */ \
+                               BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 #define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX | OR_GPCM_EAD)
+                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -150,9 +152,6 @@
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI
-#endif
 /*
  * QE UEC ethernet configuration
  */
@@ -242,7 +241,7 @@
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
                                        BATU_VS | BATU_VP)
@@ -250,7 +249,7 @@
 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_RW | \
                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
                                        | BATU_VP)
@@ -258,25 +257,25 @@
 #define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
 
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
                                BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT2U      (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                        BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
                                        BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT4U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
                                        BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT4L      CONFIG_SYS_IBAT4L
@@ -284,12 +283,7 @@
 
 /*
  * Internal Definitions
- *
- * Boot Flags
  */
-#define BOOTFLAG_COLD  0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM  0x02 /* Software reboot */
-
 #define BOOTFLASH_START        0xF0000000
 
 #define CONFIG_KM_CONSOLE_TTY  "ttyS0"
@@ -302,14 +296,13 @@
 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 #endif
 
-#ifndef CONFIG_KM_DEF_ROOTPATH
-#define CONFIG_KM_DEF_ROOTPATH         \
-       "rootpath=/opt/eldk/ppc_82xx\0"
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH     "arch=ppc_82xx\0"
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        CONFIG_KM_DEF_ENV                                               \
-       CONFIG_KM_DEF_ROOTPATH                                          \
+       CONFIG_KM_DEF_ARCH                                              \
        "dtt_bus=pca9547:70:a\0"                                        \
        "EEprom_ivm=pca9547:70:9\0"                                     \
        "newenv="                                                       \