mx6_common: Do not select esdhc DDR mode for all boards

[oweals/u-boot.git] / include / configs / ip04.h

diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 425a745408e47100f78fe86436b5baa2372a0654..2ee215f70614dfb44b7179e8247dc2936329e768 100644 (file)
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -61,7 +61,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL        0xffc2ffc2
 #define CONFIG_EBIU_AMBCTL1_VAL        0xffc2ffc2
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)
 
 
@@ -69,7 +69,6 @@
  * Network Settings
  */
 #define ADI_CMDS_NETWORK       1
-#define CONFIG_NET_MULTI       1
 #define CONFIG_HOSTNAME                IP04
 
 #define CONFIG_DRIVER_DM9000   1
@@ -78,6 +77,7 @@
 #define DM9000_IO              CONFIG_DM9000_BASE
 #define DM9000_DATA            (CONFIG_DM9000_BASE + 2)
 
+#define CONFIG_LIB_RAND
 
 /*
  * Flash Settings
@@ -116,7 +116,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@ -125,14 +124,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-       do { \
-               bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
-               bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
-               bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
-               bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
-       } while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*