Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel

[oweals/u-boot.git] / include / configs / ids8313.h

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index e930c65637be8d4c839e59c6fc27c74ab4b44047..b1d01c58f977aa0db7c38162f1d60083f03431df 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -20,23 +20,11 @@
 #define CONFIG_BOOT_RETRY_MIN          30
 #define CONFIG_RESET_TO_RETRY
 
-#define CONFIG_SYS_IMMR                0xF0000000
-
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
-
 #define CONFIG_SYS_SICRH       0x00000000
 #define CONFIG_SYS_SICRL       (SICRL_LBC | SICRL_SPI_D)
 
 #define CONFIG_HWCONFIG
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK |\
-                                HID0_ENABLE_INSTRUCTION_CACHE |\
-                                HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2        (HID2_HBE | 0x00020000)
-
 /*
  * Definitions for initial stack pointer and data area (in DCACHE )
  */
@@ -48,26 +36,13 @@
                                         - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC           LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR            (0x00040000 |\
-                                        (0xFF << LBCR_BMT_SHIFT) |\
-                                        0xF)
-
-#define CONFIG_SYS_LBC_MRTPR           0x20000000
-
 /*
  * Internal Definitions
  */
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
 
 /*
  * Manually set up DDR parameters,
@@ -142,17 +117,7 @@
 #define CONFIG_SYS_FLASH_BASE          0xFF800000
 #define CONFIG_SYS_FLASH_SIZE          8
 
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
-                                        OR_GPCM_SCY_10 |\
-                                        OR_GPCM_EHTR |\
-                                        OR_GPCM_TRLX |\
-                                        OR_GPCM_CSNT |\
-                                        OR_GPCM_EAD)
+
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_MAX_FLASH_SECT      128
 
@@ -170,21 +135,6 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
 #define NAND_CACHE_PAGES               64
 
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE) |\
-                                (2<<BR_DECC_SHIFT) |\
-                                BR_PS_8 |\
-                                BR_MS_FCM |\
-                                BR_V)
-
-#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000 |\
-                                OR_FCM_PGS |\
-                                OR_FCM_CSCT |\
-                                OR_FCM_CST |\
-                                OR_FCM_CHT |\
-                                OR_FCM_SCY_4 |\
-                                OR_FCM_TRLX |\
-                                OR_FCM_EHTR |\
-                                OR_FCM_RST)
 
 /*
  * MRAM setup
@@ -194,12 +144,6 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_MRAM_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM          0xFFFE0C74
 
 /*
  * CPLD setup
@@ -209,12 +153,6 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_CPLD_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM          0xFFFF8814
 
 /*
  * HW-Watchdog